From b4173387dd0adb27cc267b22dc57258d44fafa84 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 8 Mar 2012 17:23:56 -0800
Subject: fpga: fix custom defs in some top level makefiles

---
 usrp2/top/B100/Makefile.B100 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'usrp2/top/B100/Makefile.B100')

diff --git a/usrp2/top/B100/Makefile.B100 b/usrp2/top/B100/Makefile.B100
index 3cdbb62c0..48dc7dfd3 100644
--- a/usrp2/top/B100/Makefile.B100
+++ b/usrp2/top/B100/Makefile.B100
@@ -71,7 +71,7 @@ SYNTHESIZE_PROPERTIES = \
 "Use Clock Enable" Auto \
 "Use Synchronous Reset" Auto \
 "Use Synchronous Set" Auto \
-"Verilog Macros" "$(CUSTOM_MOD_DEFS)"
+"Verilog Macros" "$(CUSTOM_DEFS)"
 
 TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
-- 
cgit v1.2.3