aboutsummaryrefslogtreecommitdiffstats
path: root/usrp2/simple_gemac/simple_gemac_rx.v
diff options
context:
space:
mode:
authorMatt Ettus <matt@ettus.com>2010-05-27 17:31:46 -0700
committerMatt Ettus <matt@ettus.com>2010-05-27 17:31:46 -0700
commit3d06fb26c5a59451b26680b6096fca7ee37e8018 (patch)
treece172a14304474b2a46854bea6b47c2ed1f8380b /usrp2/simple_gemac/simple_gemac_rx.v
parent621ad7cc9e68b4e304b616d8f840d3a03a047c8b (diff)
parentb38d2424b1ac3242146fc9305d9e4ae80e21dede (diff)
downloaduhd-3d06fb26c5a59451b26680b6096fca7ee37e8018.tar.gz
uhd-3d06fb26c5a59451b26680b6096fca7ee37e8018.tar.bz2
uhd-3d06fb26c5a59451b26680b6096fca7ee37e8018.zip
Merge branch 'udp' into master_merge_take2
* udp: (67 commits) better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead moved fifos around, now easier to see where they are and how big bigger fifo on UDP TX path, to possibly fix overruns on decim=4 Xilinx ISE is incorrectly parsing the verilog case statement, this is a workaround pps and vita time debug pins ignore emacs backup files more debug for fixing E's better debug pins for going after cascading E's copy in wrong place copied over from quad radio just debug pin changes typo caused the tx udp chain to be disconnected moved into subdir speed up timing by ignoring the too_early error. We'll need to FIXME this later Added set time and set time at next pps. Removed the old sync pps commands, they dont make sense to use anymore. moved around regs, added a bit to allow for alternate PPS source ...
Diffstat (limited to 'usrp2/simple_gemac/simple_gemac_rx.v')
-rw-r--r--usrp2/simple_gemac/simple_gemac_rx.v5
1 files changed, 4 insertions, 1 deletions
diff --git a/usrp2/simple_gemac/simple_gemac_rx.v b/usrp2/simple_gemac/simple_gemac_rx.v
index 45ddd6dfa..b02bb0758 100644
--- a/usrp2/simple_gemac/simple_gemac_rx.v
+++ b/usrp2/simple_gemac/simple_gemac_rx.v
@@ -6,7 +6,8 @@ module simple_gemac_rx
output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
input [47:0] ucast_addr, input [47:0] mcast_addr,
input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
- output reg [15:0] pause_quanta_rcvd, output pause_rcvd );
+ output reg [15:0] pause_quanta_rcvd, output pause_rcvd,
+ output [31:0] debug );
localparam RX_IDLE = 0;
localparam RX_PREAMBLE = 1;
@@ -170,5 +171,7 @@ module simple_gemac_rx
pause_quanta_rcvd[7:0] <= rxd_d1;
assign rx_clk = GMII_RX_CLK;
+
+ assign debug = rx_state;
endmodule // simple_gemac_rx