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authorMatt Ettus <matt@ettus.com>2011-05-19 18:54:52 -0700
committerMatt Ettus <matt@ettus.com>2011-06-08 10:52:52 -0700
commit6c28203a6a8c559bae81a09be41fa5a2e06a7188 (patch)
tree90e33bc340c710e104bf1a420a6e96c6ba121f5e /usrp2/sdr_lib/rx_frontend.v
parentb88383ad6289d7056e4dc50ffc892fdd0bd115e1 (diff)
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dsp: pass 24 bit wide signals between frontend and dsp core.
Overkill, but we have the bits already, so why throw them away?
Diffstat (limited to 'usrp2/sdr_lib/rx_frontend.v')
-rw-r--r--usrp2/sdr_lib/rx_frontend.v8
1 files changed, 6 insertions, 2 deletions
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index a95110240..04b14787e 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -7,7 +7,7 @@ module rx_frontend
input [15:0] adc_a, input adc_ovf_a,
input [15:0] adc_b, input adc_ovf_b,
- output [17:0] i_out, output [17:0] q_out,
+ output [23:0] i_out, output [23:0] q_out,
input run,
output [31:0] debug
);
@@ -60,10 +60,14 @@ module rx_frontend
.in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1),
.sum(q_final), .strobe_out());
+ assign i_out = i_final;
+ assign q_out = q_final;
+
+ /*
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i
(.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q
(.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
-
+ */
endmodule // rx_frontend