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author | Josh Blum <josh@joshknows.com> | 2012-02-04 16:38:54 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2012-02-04 16:38:54 -0800 |
commit | a9d307124faa679df8180b5624e9250555306d67 (patch) | |
tree | 2bf8fc15ee0e078699ba555729aed882aeb8d266 /usrp2/sdr_lib/ddc_chain.v | |
parent | 89ce89c9aca6daf7e293b80c70e14a3e2710e137 (diff) | |
download | uhd-a9d307124faa679df8180b5624e9250555306d67.tar.gz uhd-a9d307124faa679df8180b5624e9250555306d67.tar.bz2 uhd-a9d307124faa679df8180b5624e9250555306d67.zip |
dsp rework: pass vita clears into dsp modules, unified fifo clears
Diffstat (limited to 'usrp2/sdr_lib/ddc_chain.v')
-rw-r--r-- | usrp2/sdr_lib/ddc_chain.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v index 3dee978a5..800bb5b13 100644 --- a/usrp2/sdr_lib/ddc_chain.v +++ b/usrp2/sdr_lib/ddc_chain.v @@ -19,7 +19,7 @@ module ddc_chain #(parameter BASE = 0, parameter DSPNO = 0) - (input clk, input rst, + (input clk, input rst, input clr, input set_stb, input [7:0] set_addr, input [31:0] set_data, input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, @@ -166,7 +166,7 @@ module ddc_chain (.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(ddc_chain_out[15:0]), .strobe_out()); dsp_rx_glue #(.DSPNO(DSPNO)) custom( - .clock(clk), .reset(rst), .enable(run), + .clock(clk), .reset(rst), .clear(clr), .enable(run), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .frontend_i(rx_fe_i_mux), .frontend_q(rx_fe_q_mux), .ddc_in_i(to_cordic_i), .ddc_in_q(to_cordic_q), |