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| author | Matt Ettus <matt@ettus.com> | 2012-02-02 17:57:53 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2012-02-02 17:57:53 -0800 |
| commit | 1ce83a07e188844d81db62d9e3027267fae97fb7 (patch) | |
| tree | c498f6f1ac2c79cb8bd685acc3ddaee10ad6f16c /usrp2/sdr_lib/cordic_z24.v | |
| parent | 17f5776c9cac89516a82b1e8f84f8a2dcc1a16ad (diff) | |
| download | uhd-1ce83a07e188844d81db62d9e3027267fae97fb7.tar.gz uhd-1ce83a07e188844d81db62d9e3027267fae97fb7.tar.bz2 uhd-1ce83a07e188844d81db62d9e3027267fae97fb7.zip | |
power_trig: first cut at power trigger with fixed delay
Diffstat (limited to 'usrp2/sdr_lib/cordic_z24.v')
| -rw-r--r-- | usrp2/sdr_lib/cordic_z24.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/usrp2/sdr_lib/cordic_z24.v b/usrp2/sdr_lib/cordic_z24.v index 97b7beaf7..51b074a33 100644 --- a/usrp2/sdr_lib/cordic_z24.v +++ b/usrp2/sdr_lib/cordic_z24.v @@ -119,8 +119,6 @@ module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo ); assign xo = x20[bitwidth:1]; assign yo = y20[bitwidth:1]; assign zo = z20; - //assign xo = x20[bitwidth+1:2]; // CORDIC gain is ~1.6, plus gain from rotating vectors - //assign yo = y20[bitwidth+1:2]; endmodule // cordic |