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authorJosh Blum <josh@joshknows.com>2011-07-08 12:14:53 -0700
committerJosh Blum <josh@joshknows.com>2011-07-08 12:14:53 -0700
commit4ea6f7431e09d9f27ecaa1c1b187d2c2f613e8f4 (patch)
treed2e66eb4e5f7cf7f8ab033f5482a6f2477aa88b6 /usrp2/sdr_lib/add2_and_clip_reg.v
parentdd41da159157afe417e7f3b77ba30e189eb510fe (diff)
parentfbc01138d5f943b06ce1bf3f746287b9d6c7789d (diff)
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Merge branch 'b100_shrink' into next
Diffstat (limited to 'usrp2/sdr_lib/add2_and_clip_reg.v')
-rw-r--r--usrp2/sdr_lib/add2_and_clip_reg.v25
1 files changed, 25 insertions, 0 deletions
diff --git a/usrp2/sdr_lib/add2_and_clip_reg.v b/usrp2/sdr_lib/add2_and_clip_reg.v
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+++ b/usrp2/sdr_lib/add2_and_clip_reg.v
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+
+module add2_and_clip_reg
+ #(parameter WIDTH=16)
+ (input clk,
+ input rst,
+ input [WIDTH-1:0] in1,
+ input [WIDTH-1:0] in2,
+ input strobe_in,
+ output reg [WIDTH-1:0] sum,
+ output reg strobe_out);
+
+ wire [WIDTH-1:0] sum_int;
+
+ add2_and_clip #(.WIDTH(WIDTH)) add2_and_clip (.in1(in1),.in2(in2),.sum(sum_int));
+
+ always @(posedge clk)
+ if(rst)
+ sum <= 0;
+ else if(strobe_in)
+ sum <= sum_int;
+
+ always @(posedge clk)
+ strobe_out <= strobe_in;
+
+endmodule // add2_and_clip_reg