diff options
| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /usrp2/opencores/spi/bench/verilog/CVS | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'usrp2/opencores/spi/bench/verilog/CVS')
| -rw-r--r-- | usrp2/opencores/spi/bench/verilog/CVS/Entries | 4 | ||||
| -rw-r--r-- | usrp2/opencores/spi/bench/verilog/CVS/Repository | 1 | ||||
| -rw-r--r-- | usrp2/opencores/spi/bench/verilog/CVS/Root | 1 | ||||
| -rw-r--r-- | usrp2/opencores/spi/bench/verilog/CVS/Template | 0 |
4 files changed, 6 insertions, 0 deletions
diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Entries b/usrp2/opencores/spi/bench/verilog/CVS/Entries new file mode 100644 index 000000000..68404f871 --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/CVS/Entries @@ -0,0 +1,4 @@ +/spi_slave_model.v/1.2/Wed Mar 26 16:00:03 2003// +/tb_spi_top.v/1.6/Mon Mar 15 17:46:04 2004// +/wb_master_model.v/1.1.1.1/Wed Jun 12 15:45:23 2002// +D diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Repository b/usrp2/opencores/spi/bench/verilog/CVS/Repository new file mode 100644 index 000000000..78a3c4a9f --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/CVS/Repository @@ -0,0 +1 @@ +spi/bench/verilog diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Root b/usrp2/opencores/spi/bench/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/usrp2/opencores/spi/bench/verilog/CVS/Template b/usrp2/opencores/spi/bench/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/usrp2/opencores/spi/bench/verilog/CVS/Template |