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| author | Matt Ettus <matt@ettus.com> | 2010-08-25 19:00:02 -0700 |
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| committer | Matt Ettus <matt@ettus.com> | 2010-08-25 19:00:02 -0700 |
| commit | 9e2e78642251ee9e024461becfd70a75b11d818a (patch) | |
| tree | 4dd389161082c2ca4add7137af4d8004e63ed2a4 /usrp2/opencores/i2c/sim/i2c_verilog | |
| parent | 2e526a8411f97654a2e87bdd1e524729da71315e (diff) | |
| download | uhd-9e2e78642251ee9e024461becfd70a75b11d818a.tar.gz uhd-9e2e78642251ee9e024461becfd70a75b11d818a.tar.bz2 uhd-9e2e78642251ee9e024461becfd70a75b11d818a.zip | |
SWAP DAC A and B, invert B to match schematics
Diffstat (limited to 'usrp2/opencores/i2c/sim/i2c_verilog')
0 files changed, 0 insertions, 0 deletions