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author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:00:25 -0700 |
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committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:07:59 -0700 |
commit | 1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (patch) | |
tree | 04f94ef4f7f06a210f7532592829332c7f2621f0 /usrp2/opencores/aemb/sim/cversim | |
parent | 7b8f65256b5ea300187ebb6a359df2fa707a295d (diff) | |
parent | 42fc55415af499980901c7787f44c7e74b4a9ce1 (diff) | |
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Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
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Diffstat (limited to 'usrp2/opencores/aemb/sim/cversim')
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