Merge branch 'master' into u1e_merge_with_master

* master:
  get rid of some warnings by declaring setting reg width
  added width parameter to avoid warnings (thanks IJB) and default value parameter
  added pragmas suggested by Ian Buckley to help ISE12 synthesis
  get rid of old CVS linkage
  settings bus to dsp_clk now uses clock crossing fifo
  remove files for old prototypes, they were confusing people
  revert commit 9899b81f920 which should have improved timing but didn't

Conflicts:
	usrp2/control_lib/setting_reg.v
	usrp2/top/u2_core/u2_core.v
	usrp2/top/u2_rev3/Makefile

9 files changed, 6 insertions, 46 deletions

diff --git a/usrp2/opencores/aemb/rtl/CVS/Entries b/usrp2/opencores/aemb/rtl/CVS/Entries
deleted file mode 100644
index 428c5622d..000000000
--- a/usrp2/opencores/aemb/rtl/CVS/Entries
+++ /dev/null
@@ -1 +0,0 @@
-D/verilog////
diff --git a/usrp2/opencores/aemb/rtl/CVS/Repository b/usrp2/opencores/aemb/rtl/CVS/Repository
deleted file mode 100644
index e2c1eab77..000000000
--- a/usrp2/opencores/aemb/rtl/CVS/Repository
+++ /dev/null
@@ -1 +0,0 @@
-aemb/rtl
diff --git a/usrp2/opencores/aemb/rtl/CVS/Root b/usrp2/opencores/aemb/rtl/CVS/Root
deleted file mode 100644
index 44b2aa23b..000000000
--- a/usrp2/opencores/aemb/rtl/CVS/Root
+++ /dev/null
@@ -1 +0,0 @@
-:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/usrp2/opencores/aemb/rtl/CVS/Template b/usrp2/opencores/aemb/rtl/CVS/Template
deleted file mode 100644
index e69de29bb..000000000
--- a/usrp2/opencores/aemb/rtl/CVS/Template
+++ /dev/null
diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Entries b/usrp2/opencores/aemb/rtl/verilog/CVS/Entries
deleted file mode 100644
index f17d70235..000000000
--- a/usrp2/opencores/aemb/rtl/verilog/CVS/Entries
+++ /dev/null
@@ -1,38 +0,0 @@
-/aeMB2_aslu.v/1.10/Tue May 20 18:13:50 2008//
-/aeMB2_bpcu.v/1.5/Tue May 20 18:13:50 2008//
-/aeMB2_brcc.v/1.3/Tue May 20 18:13:50 2008//
-/aeMB2_bsft.v/1.3/Tue May 20 18:13:50 2008//
-/aeMB2_ctrl.v/1.7/Tue May 20 18:13:51 2008//
-/aeMB2_dparam.v/1.1/Tue May 20 18:13:51 2008//
-/aeMB2_dwbif.v/1.7/Tue May 20 18:13:51 2008//
-/aeMB2_edk32.v/1.8/Tue May 20 18:13:51 2008//
-/aeMB2_edk62.v/1.8/Tue May 20 18:13:51 2008//
-/aeMB2_exec.v/1.4/Tue May 20 18:13:51 2008//
-/aeMB2_gprf.v/1.4/Tue May 20 18:13:51 2008//
-/aeMB2_iche.v/1.5/Tue May 20 18:13:51 2008//
-/aeMB2_idmx.v/1.5/Tue May 20 18:13:51 2008//
-/aeMB2_intu.v/1.7/Tue May 20 18:13:51 2008//
-/aeMB2_iwbif.v/1.5/Tue May 20 18:13:51 2008//
-/aeMB2_memif.v/1.3/Tue May 20 18:13:51 2008//
-/aeMB2_mult.v/1.5/Tue May 20 18:13:51 2008//
-/aeMB2_ofid.v/1.2/Tue May 20 18:13:51 2008//
-/aeMB2_opmx.v/1.3/Tue May 20 18:13:51 2008//
-/aeMB2_pipe.v/1.4/Tue May 20 18:13:51 2008//
-/aeMB2_regf.v/1.3/Tue May 20 18:13:51 2008//
-/aeMB2_regs.v/1.4/Tue May 20 18:13:51 2008//
-/aeMB2_sfrf.v/1.2/Tue May 20 18:13:51 2008//
-/aeMB2_sim.v/1.2/Tue May 20 18:13:51 2008//
-/aeMB2_sparam.v/1.2/Tue May 20 18:13:51 2008//
-/aeMB2_spsram.v/1.1/Tue May 20 18:13:51 2008//
-/aeMB2_sysc.v/1.5/Tue May 20 18:13:51 2008//
-/aeMB2_tpsram.v/1.3/Tue May 20 18:13:51 2008//
-/aeMB2_xslif.v/1.7/Tue May 20 18:13:52 2008//
-/aeMB_bpcu.v/1.4/Thu Sep 11 02:11:12 2008//
-/aeMB_core.v/1.9/Thu Sep 11 02:11:12 2008//
-/aeMB_ctrl.v/1.10/Thu Sep 11 02:11:12 2008//
-/aeMB_edk32.v/1.14/Thu Sep 11 02:11:12 2008//
-/aeMB_ibuf.v/1.10/Thu Sep 11 02:11:12 2008//
-/aeMB_regf.v/1.3/Thu Sep 11 02:11:12 2008//
-/aeMB_sim.v/1.2/Thu Jan 22 05:50:30 2009//
-/aeMB_xecu.v/1.12/Thu Sep 11 02:11:12 2008//
-D
diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Repository b/usrp2/opencores/aemb/rtl/verilog/CVS/Repository
deleted file mode 100644
index a9de19556..000000000
--- a/usrp2/opencores/aemb/rtl/verilog/CVS/Repository
+++ /dev/null
@@ -1 +0,0 @@
-aemb/rtl/verilog
diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Root b/usrp2/opencores/aemb/rtl/verilog/CVS/Root
deleted file mode 100644
index 44b2aa23b..000000000
--- a/usrp2/opencores/aemb/rtl/verilog/CVS/Root
+++ /dev/null
@@ -1 +0,0 @@
-:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/usrp2/opencores/aemb/rtl/verilog/CVS/Template b/usrp2/opencores/aemb/rtl/verilog/CVS/Template
deleted file mode 100644
index e69de29bb..000000000
--- a/usrp2/opencores/aemb/rtl/verilog/CVS/Template
+++ /dev/null
diff --git a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
index 9ac45299b..7fe108957 100644
--- a/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
+++ b/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
@@ -146,9 +146,12 @@ module aeMB_regf (/*AUTOARG*/
    // LUT RAM implementation is smaller and faster. R0 gets written
    // during reset with 0x00 and doesn't change after.
    
-   reg [31:0] 	 mARAM[0:31],
-		 mBRAM[0:31],
-		 mDRAM[0:31];
+   //synthesis attribute ram_style of mARAM is distributed
+   reg [31:0] 	 mARAM[0:31]; 
+   //synthesis attribute ram_style of mBRAM is distributed
+   reg [31:0] 	 mBRAM[0:31];
+   //synthesis attribute ram_style of mDRAM is distributed
+   reg [31:0] 	 mDRAM[0:31];
 
    wire [31:0] 	 rREGW = mDRAM[rRW];   
    wire [31:0] 	 rREGD = mDRAM[rRD];