fifo36_mux now has shortfifos on the input ports as well as output

2 files changed, 3 insertions, 6 deletions

diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v
index cf8b6e861..9a8e37ce9 100644
--- a/usrp2/gpmc/fifo_to_gpmc_async.v
+++ b/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -1,9 +1,4 @@
 
-// Assumes an asynchronous GPMC cycle
-//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
-//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
-//   If there is a bus error, we should be reset
-
 module fifo_to_gpmc_async
   (input clk, input reset, input clear,
    input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v
index 053df5b18..02bf45b8a 100644
--- a/usrp2/gpmc/gpmc_async.v
+++ b/usrp2/gpmc/gpmc_async.v
@@ -215,7 +215,9 @@ module gpmc_async
 
 wire [0:17] dummy18;
 
-assign debug = {dummy18, timedrx_src_rdy_int, timedrx_dst_rdy_int,
+assign debug = {8'd0,
+		test_rate,
+		pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int,
 		timedrx_src_rdy, timedrx_dst_rdy,
 		testrx_src_rdy, testrx_dst_rdy,
 		rx_src_rdy, rx_dst_rdy,