From 98a1a03de054306f57be68e1b498c1d39a954472 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Fri, 25 Feb 2011 15:17:31 -0800 Subject: fifo36_mux now has shortfifos on the input ports as well as output --- usrp2/gpmc/fifo_to_gpmc_async.v | 5 ----- usrp2/gpmc/gpmc_async.v | 4 +++- 2 files changed, 3 insertions(+), 6 deletions(-) (limited to 'usrp2/gpmc') diff --git a/usrp2/gpmc/fifo_to_gpmc_async.v b/usrp2/gpmc/fifo_to_gpmc_async.v index cf8b6e861..9a8e37ce9 100644 --- a/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/usrp2/gpmc/fifo_to_gpmc_async.v @@ -1,9 +1,4 @@ -// Assumes an asynchronous GPMC cycle -// If a packet bigger or smaller than we are told is sent, behavior is undefined. -// If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error. -// If there is a bus error, we should be reset - module fifo_to_gpmc_async (input clk, input reset, input clear, input [17:0] data_i, input src_rdy_i, output dst_rdy_o, diff --git a/usrp2/gpmc/gpmc_async.v b/usrp2/gpmc/gpmc_async.v index 053df5b18..02bf45b8a 100644 --- a/usrp2/gpmc/gpmc_async.v +++ b/usrp2/gpmc/gpmc_async.v @@ -215,7 +215,9 @@ module gpmc_async wire [0:17] dummy18; -assign debug = {dummy18, timedrx_src_rdy_int, timedrx_dst_rdy_int, +assign debug = {8'd0, + test_rate, + pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int, timedrx_src_rdy, timedrx_dst_rdy, testrx_src_rdy, testrx_dst_rdy, rx_src_rdy, rx_dst_rdy, -- cgit v1.2.3