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authorMatt Ettus <matt@ettus.com>2010-06-08 14:16:22 -0700
committerMatt Ettus <matt@ettus.com>2010-06-08 14:16:22 -0700
commit724af67a222aca01207cda9e0e4a8ce33217b7b8 (patch)
tree0723810799c76e5b471e65e26f5d1f8fdfa3c2f3 /usrp2/gpmc/fifo_watcher.v
parent6eb6050269f469b982843b526eff80b37e8c5f3b (diff)
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debug pins
Diffstat (limited to 'usrp2/gpmc/fifo_watcher.v')
-rw-r--r--usrp2/gpmc/fifo_watcher.v4
1 files changed, 3 insertions, 1 deletions
diff --git a/usrp2/gpmc/fifo_watcher.v b/usrp2/gpmc/fifo_watcher.v
index 4bba142b0..fe4e35de3 100644
--- a/usrp2/gpmc/fifo_watcher.v
+++ b/usrp2/gpmc/fifo_watcher.v
@@ -4,13 +4,15 @@ module fifo_watcher
(input clk, input reset, input clear,
input src_rdy1, input dst_rdy1, input sof1, input eof1,
input src_rdy2, input dst_rdy2, input sof2, input eof2,
- output reg have_packet, output [15:0] length, output reg bus_error);
+ output reg have_packet, output [15:0] length, output reg bus_error,
+ output [31:0] debug);
wire write = src_rdy1 & dst_rdy1 & eof1;
wire read = src_rdy2 & dst_rdy2 & eof2;
wire have_packet_int;
reg [15:0] counter;
wire [4:0] pkt_count;
+ assign debug = pkt_count;
fifo_short #(.WIDTH(16)) frame_lengths
(.clk(clk), .reset(reset), .clear(clear),