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| author | Matt Ettus <matt@ettus.com> | 2011-03-18 16:11:02 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:21 -0700 |
| commit | a4dc4a539a61d94a2d18b4576371d230c0dc6514 (patch) | |
| tree | 115f01c6db3d1684d22368fb7bd0887963966778 /usrp2/fifo | |
| parent | ac3e42d1053772f324245dfff23eadcc7c6135cd (diff) | |
| download | uhd-a4dc4a539a61d94a2d18b4576371d230c0dc6514.tar.gz uhd-a4dc4a539a61d94a2d18b4576371d230c0dc6514.tar.bz2 uhd-a4dc4a539a61d94a2d18b4576371d230c0dc6514.zip | |
u1p: use 18 bit fifos and use full size of a block ram in the tx path
Diffstat (limited to 'usrp2/fifo')
| -rw-r--r-- | usrp2/fifo/fifo_2clock.v | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/usrp2/fifo/fifo_2clock.v b/usrp2/fifo/fifo_2clock.v index 34c85ccb4..f3ed5324f 100644 --- a/usrp2/fifo/fifo_2clock.v +++ b/usrp2/fifo/fifo_2clock.v @@ -14,7 +14,8 @@ module fifo_2clock assign src_rdy_o = ~empty; assign write = src_rdy_i & dst_rdy_o; assign read = src_rdy_o & dst_rdy_i; - + wire dummy; + generate if(WIDTH==36) if(SIZE==9) @@ -37,12 +38,16 @@ module fifo_2clock (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if((WIDTH==19)|(WIDTH==18)) - if(SIZE==4) - fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==19) & (SIZE==4)) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==18) & (SIZE==4)) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; |