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author | Josh Blum <josh@joshknows.com> | 2011-01-11 12:16:33 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2011-01-11 12:24:38 -0800 |
commit | d7a8b451d27553b0313917e66255214822ed492b (patch) | |
tree | 6ba26deac5d0d061d7dcc3f4e0d9e59a9c553e8a /usrp2/fifo/valve36.v | |
parent | acec75d5f0a20701cfd357ebefe6e59a35f4a948 (diff) | |
download | uhd-d7a8b451d27553b0313917e66255214822ed492b.tar.gz uhd-d7a8b451d27553b0313917e66255214822ed492b.tar.bz2 uhd-d7a8b451d27553b0313917e66255214822ed492b.zip |
xbar and valve: fix switching delayed by active signal
Diffstat (limited to 'usrp2/fifo/valve36.v')
-rw-r--r-- | usrp2/fifo/valve36.v | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/usrp2/fifo/valve36.v b/usrp2/fifo/valve36.v index b4b23e5a6..d45eee497 100644 --- a/usrp2/fifo/valve36.v +++ b/usrp2/fifo/valve36.v @@ -7,7 +7,8 @@ module valve36 output [35:0] data_o, output src_rdy_o, input dst_rdy_i); reg shutoff_int, active; - + wire active_next = (src_rdy_i & dst_rdy_o)? ~data_i[33] : active; + assign data_o = data_i; assign dst_rdy_o = shutoff_int ? 1'b1 : dst_rdy_i; @@ -16,13 +17,13 @@ module valve36 always @(posedge clk) if(reset | clear) active <= 0; - else if(src_rdy_i & dst_rdy_o) - active <= ~data_i[33]; + else + active <= active_next; always @(posedge clk) if(reset | clear) shutoff_int <= 0; - else if(~active) + else if(~active_next) shutoff_int <= shutoff; endmodule // valve36 |