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| author | Matt Ettus <matt@ettus.com> | 2011-06-12 14:03:42 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-12 14:03:42 -0700 |
| commit | cd9308eb81fd37fcd5142d49c10741f107e6b657 (patch) | |
| tree | 42a80b07cd7d438330c6e7875a367c59cc6f3b93 /usrp2/fifo/fifo_2clock.v | |
| parent | c0fadece89314f3a00892122c28caf187ce1a717 (diff) | |
| download | uhd-cd9308eb81fd37fcd5142d49c10741f107e6b657.tar.gz uhd-cd9308eb81fd37fcd5142d49c10741f107e6b657.tar.bz2 uhd-cd9308eb81fd37fcd5142d49c10741f107e6b657.zip | |
u1e: new 2 clock fifo, 18 bits by 1K
Diffstat (limited to 'usrp2/fifo/fifo_2clock.v')
| -rw-r--r-- | usrp2/fifo/fifo_2clock.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/usrp2/fifo/fifo_2clock.v b/usrp2/fifo/fifo_2clock.v index 756ad508f..c6aaf34dc 100644 --- a/usrp2/fifo/fifo_2clock.v +++ b/usrp2/fifo/fifo_2clock.v @@ -65,6 +65,11 @@ module fifo_2clock (.rst(arst), .wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if ((WIDTH==18) & (SIZE==10)) + fifo_xlnx_1Kx18_2clk fifo_xlnx_1Kx18_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; |