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authorJosh Blum <josh@joshknows.com>2010-12-11 17:44:27 -0800
committerJosh Blum <josh@joshknows.com>2010-12-11 17:44:27 -0800
commit179c651716798bd7b3aaa74c6a546f041e2e3688 (patch)
tree22930153d396cb1745884b1b7f120cc74847debe /usrp2/fifo/dsp_framer36.v
parent6ab84f8f1a51ecd7eb9562f9e2fb52f893721c43 (diff)
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packet_router: raise enable for bram reads the cycle before as well
Diffstat (limited to 'usrp2/fifo/dsp_framer36.v')
-rw-r--r--usrp2/fifo/dsp_framer36.v3
1 files changed, 2 insertions, 1 deletions
diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v
index fbdc9fbd7..e44f91305 100644
--- a/usrp2/fifo/dsp_framer36.v
+++ b/usrp2/fifo/dsp_framer36.v
@@ -29,6 +29,7 @@ module dsp_framer36
//The header is generated here from the count.
wire [31:0] dsp_frm_data_bram;
wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00};
+ wire dsp_frm_enb = (dsp_frm_state == DSP_FRM_STATE_WRITE)? (out_ready & out_valid) : 1'b1;
assign out_data =
(dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : (
(dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : (
@@ -44,7 +45,7 @@ module dsp_framer36
.ENA(inp_ready),.SSRA(0),.WEA(inp_ready),
//port B = DSP framer interface (reads from BRAM)
.DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0),
- .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0)
+ .ENB(dsp_frm_enb),.SSRB(0),.WEB(1'b0)
);
always @(posedge clk)