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author | Matt Ettus <matt@ettus.com> | 2010-10-21 13:08:23 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-10-21 13:08:23 -0700 |
commit | c32f4fbc8973633280249399d5d5a937ef0f1f3e (patch) | |
tree | d78753a0e4d4477393c5b750a83825a35225fd21 /usrp2/extramfifo/refill_randomizer.v | |
parent | ee03f1d4acf5c7d3359c86baba5085660d63ebae (diff) | |
download | uhd-c32f4fbc8973633280249399d5d5a937ef0f1f3e.tar.gz uhd-c32f4fbc8973633280249399d5d5a937ef0f1f3e.tar.bz2 uhd-c32f4fbc8973633280249399d5d5a937ef0f1f3e.zip |
should combine the randomizer with flow_control
Diffstat (limited to 'usrp2/extramfifo/refill_randomizer.v')
-rw-r--r-- | usrp2/extramfifo/refill_randomizer.v | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/usrp2/extramfifo/refill_randomizer.v b/usrp2/extramfifo/refill_randomizer.v new file mode 100644 index 000000000..0b30f4049 --- /dev/null +++ b/usrp2/extramfifo/refill_randomizer.v @@ -0,0 +1,66 @@ +// +// EMI mitigation. +// Process FULL flag from FIFO so that de-assertion +// (FIFO now not FULL) is delayed by a pseudo random +// value, but assertion is passed straight through. +// + + +module refill_randomizer + #(parameter BITS=7) + ( + input clk, + input rst, + input full_in, + output full_out + ); + + wire feedback; + reg full_last; + wire full_deasserts; + reg [6:0] shift_reg; + reg [6:0] count; + reg delayed_fall; + + + always @(posedge clk) + full_last <= full_in; + + assign full_deasserts = full_last & ~full_in; + + // 7 bit LFSR + always @(posedge clk) + if (rst) + shift_reg <= 7'b1; + else + if (full_deasserts) + shift_reg <= {shift_reg[5:0],feedback}; + + assign feedback = ^(shift_reg & 7'h41); + + always @(posedge clk) + if (rst) + begin + count <= 1; + delayed_fall <= 1; + end + else if (full_deasserts) + begin + count <= shift_reg; + delayed_fall <= 1; + end + else if (count == 1) + begin + count <= 1; + delayed_fall <= 0; + end + else + begin + count <= count - 1; + delayed_fall <= 1; + end + + // Full_out goes instantly high if full_in does. However its fall is delayed. + assign full_out = (full_in == 1) || (full_last == 1) || delayed_fall; + +endmodule
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