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| author | Matt Ettus <matt@ettus.com> | 2010-07-14 17:01:25 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-14 17:01:25 -0700 |
| commit | 886606f55da066b66d214e512a2226b19a1073df (patch) | |
| tree | 7a55c10091023632f83833a782549ab57cd8cb7e /usrp2/extramfifo/fifo_extram_tb.build | |
| parent | bd455159a0b60eb2c496322d0f80c3ca77d838f6 (diff) | |
| download | uhd-886606f55da066b66d214e512a2226b19a1073df.tar.gz uhd-886606f55da066b66d214e512a2226b19a1073df.tar.bz2 uhd-886606f55da066b66d214e512a2226b19a1073df.zip | |
get it to build
Diffstat (limited to 'usrp2/extramfifo/fifo_extram_tb.build')
| -rwxr-xr-x[-rw-r--r--] | usrp2/extramfifo/fifo_extram_tb.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/extramfifo/fifo_extram_tb.build b/usrp2/extramfifo/fifo_extram_tb.build index e87217e5c..5607c8691 100644..100755 --- a/usrp2/extramfifo/fifo_extram_tb.build +++ b/usrp2/extramfifo/fifo_extram_tb.build @@ -1 +1 @@ -iverilog -y ../../models -y ../../models/CY7C1356C -y . -y ../../control_lib/ -y ../../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v +iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v |