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| author | Ian Buckley <ianb@server2.(none)> | 2010-07-29 21:25:26 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 11:36:09 -0800 |
| commit | fb73ea172526319803756b985dd3c104881304b1 (patch) | |
| tree | 5f5a6d4da4f24a317395c86586e49ec6b9bb414a /usrp2/extramfifo/ext_fifo_tb.prj | |
| parent | d0742cf2a5285ed08d49e16948d8227414247f6a (diff) | |
| download | uhd-fb73ea172526319803756b985dd3c104881304b1.tar.gz uhd-fb73ea172526319803756b985dd3c104881304b1.tar.bz2 uhd-fb73ea172526319803756b985dd3c104881304b1.zip | |
Checkpoint checkin.
Loopback is running via the external ZBT SRAM...HOWEVER, its not running well, its stable but the data is corrupted sometimes.
Not clear if its a logic or AC timing/SI issue yet.
Diffstat (limited to 'usrp2/extramfifo/ext_fifo_tb.prj')
| -rw-r--r-- | usrp2/extramfifo/ext_fifo_tb.prj | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/usrp2/extramfifo/ext_fifo_tb.prj b/usrp2/extramfifo/ext_fifo_tb.prj new file mode 100644 index 000000000..a11a15b2f --- /dev/null +++ b/usrp2/extramfifo/ext_fifo_tb.prj @@ -0,0 +1,9 @@ +verilog work "./ext_fifo_tb.v" +verilog work "./ext_fifo.v" +verilog work "./nobl_fifo.v" +verilog work "./nobl_if.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_36to18.v" +verilog work "../coregen/fifo_xlnx_512x36_2clk_18to36.v" +verilog work "../models/CY7C1356C/cy1356.v" +verilog work "../models/idt71v65603s150.v" +verilog work "$XILINX/verilog/src/glbl.v" |