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| author | Ian Buckley <ianb@server2.(none)> | 2010-08-19 17:28:07 -0700 |
|---|---|---|
| committer | Ian Buckley <ianb@server2.(none)> | 2010-08-19 17:28:07 -0700 |
| commit | 0e8a978c90c5793374861f29f72517f0070e596a (patch) | |
| tree | eebc1ebc8c23b5465fa6effa062c8ae18de5847b /usrp2/extramfifo/ext_fifo_tb.cmd | |
| parent | 05b1c0b5cf947e230a012f225cf51f0ea81132d2 (diff) | |
| download | uhd-0e8a978c90c5793374861f29f72517f0070e596a.tar.gz uhd-0e8a978c90c5793374861f29f72517f0070e596a.tar.bz2 uhd-0e8a978c90c5793374861f29f72517f0070e596a.zip | |
Added a bunch of debug signals.
Diffstat (limited to 'usrp2/extramfifo/ext_fifo_tb.cmd')
| -rw-r--r-- | usrp2/extramfifo/ext_fifo_tb.cmd | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/extramfifo/ext_fifo_tb.cmd b/usrp2/extramfifo/ext_fifo_tb.cmd index b0ab830dc..521f88f21 100644 --- a/usrp2/extramfifo/ext_fifo_tb.cmd +++ b/usrp2/extramfifo/ext_fifo_tb.cmd @@ -1,6 +1,7 @@ /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v -y . -y ../coregen/ +-y ../fifo -y ../models -y /home/ianb/usrp-fpga/usrp2/sdr_lib -y /home/ianb/usrp-fpga/usrp2/control_lib |