From 0e8a978c90c5793374861f29f72517f0070e596a Mon Sep 17 00:00:00 2001
From: Ian Buckley <ianb@server2.(none)>
Date: Thu, 19 Aug 2010 17:28:07 -0700
Subject: Added a bunch of debug signals.

---
 usrp2/extramfifo/ext_fifo_tb.cmd | 1 +
 1 file changed, 1 insertion(+)

(limited to 'usrp2/extramfifo/ext_fifo_tb.cmd')

diff --git a/usrp2/extramfifo/ext_fifo_tb.cmd b/usrp2/extramfifo/ext_fifo_tb.cmd
index b0ab830dc..521f88f21 100644
--- a/usrp2/extramfifo/ext_fifo_tb.cmd
+++ b/usrp2/extramfifo/ext_fifo_tb.cmd
@@ -1,6 +1,7 @@
 /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v
 -y .
 -y ../coregen/
+-y ../fifo
 -y ../models
 -y /home/ianb/usrp-fpga/usrp2/sdr_lib
 -y /home/ianb/usrp-fpga/usrp2/control_lib
-- 
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