Merge branch 'master' into u1e_merge_with_master

* master:
  get rid of some warnings by declaring setting reg width
  added width parameter to avoid warnings (thanks IJB) and default value parameter
  added pragmas suggested by Ian Buckley to help ISE12 synthesis
  get rid of old CVS linkage
  settings bus to dsp_clk now uses clock crossing fifo
  remove files for old prototypes, they were confusing people
  revert commit 9899b81f920 which should have improved timing but didn't

Conflicts:
	usrp2/control_lib/setting_reg.v
	usrp2/top/u2_core/u2_core.v
	usrp2/top/u2_rev3/Makefile

1 files changed, 4 insertions, 2 deletions

diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v
index c8aff230f..3d3bb65e5 100644
--- a/usrp2/control_lib/setting_reg.v
+++ b/usrp2/control_lib/setting_reg.v
@@ -1,9 +1,11 @@
 
 
 module setting_reg
-  #(parameter my_addr = 0, parameter at_reset=32'd0)
+  #(parameter my_addr = 0, 
+    parameter width = 32,
+    parameter at_reset=32'd0)
     (input clk, input rst, input strobe, input wire [7:0] addr,
-     input wire [31:0] in, output reg [31:0] out, output reg changed);
+     input wire [31:0] in, output reg [width-1:0] out, output reg changed);
    
    always @(posedge clk)
      if(rst)