From f85e6c6d2f8ed6224eac44ca22d2701600e8a36e Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Thu, 13 May 2010 13:37:39 -0700 Subject: revert commit 9899b81f920 which should have improved timing but didn't --- usrp2/control_lib/settings_bus.v | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) (limited to 'usrp2/control_lib') diff --git a/usrp2/control_lib/settings_bus.v b/usrp2/control_lib/settings_bus.v index aec179516..d01a30ab4 100644 --- a/usrp2/control_lib/settings_bus.v +++ b/usrp2/control_lib/settings_bus.v @@ -10,7 +10,8 @@ module settings_bus input wb_stb_i, input wb_we_i, output reg wb_ack_o, - output reg strobe, + input sys_clk, + output strobe, output reg [7:0] addr, output reg [31:0] data); @@ -19,18 +20,18 @@ module settings_bus always @(posedge wb_clk) if(wb_rst) begin - strobe <= 1'b0; + stb_int <= 1'b0; addr <= 8'd0; data <= 32'd0; end - else if(wb_we_i & wb_stb_i & ~wb_ack_o) + else if(wb_we_i & wb_stb_i) begin - strobe <= 1'b1; + stb_int <= 1'b1; addr <= wb_adr_i[9:2]; data <= wb_dat_i; end else - strobe <= 1'b0; + stb_int <= 1'b0; always @(posedge wb_clk) if(wb_rst) @@ -38,4 +39,11 @@ module settings_bus else wb_ack_o <= wb_stb_i & ~wb_ack_o; + always @(posedge wb_clk) + stb_int_d1 <= stb_int; + + //assign strobe = stb_int & ~stb_int_d1; + assign strobe = stb_int & wb_ack_o; + endmodule // settings_bus + -- cgit v1.2.3 From 8214a30d10bbe30d04f74acca4bd683dc084f5df Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Tue, 18 May 2010 12:36:19 -0700 Subject: added width parameter to avoid warnings (thanks IJB) and default value parameter --- usrp2/control_lib/setting_reg.v | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'usrp2/control_lib') diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v index ccbaa3d2e..3d3bb65e5 100644 --- a/usrp2/control_lib/setting_reg.v +++ b/usrp2/control_lib/setting_reg.v @@ -1,14 +1,16 @@ module setting_reg - #(parameter my_addr = 0) + #(parameter my_addr = 0, + parameter width = 32, + parameter at_reset=32'd0) (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); + input wire [31:0] in, output reg [width-1:0] out, output reg changed); always @(posedge clk) if(rst) begin - out <= 32'd0; + out <= at_reset; changed <= 1'b0; end else -- cgit v1.2.3