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authorMatt Ettus <matt@ettus.com>2010-05-18 15:01:09 -0700
committerMatt Ettus <matt@ettus.com>2010-05-18 15:01:09 -0700
commitec0f7e9afdae0136752062e5bceb50e1c68d985f (patch)
tree44cac2de7f336772abb9bbf2d5e4e285b0dfb435 /usrp2/control_lib
parentac32c1fef042a3041a37a8c68e505156cba31484 (diff)
parent621ad7cc9e68b4e304b616d8f840d3a03a047c8b (diff)
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Merge branch 'master' into udp
Remove CVS files, warning removal on setting reg width, aeMB synthesis pragmas Conflicts: usrp2/control_lib/setting_reg.v usrp2/top/u2_core/u2_core.v usrp2/top/u2_rev3/Makefile
Diffstat (limited to 'usrp2/control_lib')
-rw-r--r--usrp2/control_lib/setting_reg.v6
1 files changed, 4 insertions, 2 deletions
diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v
index c8aff230f..3d3bb65e5 100644
--- a/usrp2/control_lib/setting_reg.v
+++ b/usrp2/control_lib/setting_reg.v
@@ -1,9 +1,11 @@
module setting_reg
- #(parameter my_addr = 0, parameter at_reset=32'd0)
+ #(parameter my_addr = 0,
+ parameter width = 32,
+ parameter at_reset=32'd0)
(input clk, input rst, input strobe, input wire [7:0] addr,
- input wire [31:0] in, output reg [31:0] out, output reg changed);
+ input wire [31:0] in, output reg [width-1:0] out, output reg changed);
always @(posedge clk)
if(rst)