spi core: ready logic low one cycle earlier

FIFO ctrl can poke registers every other cycle,
the extra time to register not ready for spi core was too long.
And it with ~trigger to get the not-ready one cycle earlier,
so FIFO ctrl can block on the 2nd potential spi transaction.

1 files changed, 1 insertions, 1 deletions

diff --git a/usrp2/control_lib/simple_spi_core.v b/usrp2/control_lib/simple_spi_core.v
index 208fceb23..3c0ed60b9 100644
--- a/usrp2/control_lib/simple_spi_core.v
+++ b/usrp2/control_lib/simple_spi_core.v
@@ -106,7 +106,7 @@ module simple_spi_core
     reg [2:0] state;
 
     reg ready_reg;
-    assign ready = ready_reg;
+    assign ready = ready_reg && ~trigger_spi;
 
     //serial clock either idles or is in one of two clock states
     reg sclk_reg;