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authorJosh Blum <josh@joshknows.com>2012-03-06 16:30:24 -0800
committerJosh Blum <josh@joshknows.com>2012-03-16 11:29:18 -0700
commitc7adcbe4a61235eff762195e35bf990a1a409e12 (patch)
tree86204e497c3b7bfdc688b05b4b978031b85cd7f9 /usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
parent46c612ea97d41745f6477ddb4cb024e06be8ed8c (diff)
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fifo ctrl: spi core work, fifo ctrl perifs, usrp2 support
Continued work on simple spi core. Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl. Copied the implementation into usrp2 core.
Diffstat (limited to 'usrp2/control_lib/settings_readback_bus_fifo_ctrl.v')
-rw-r--r--usrp2/control_lib/settings_readback_bus_fifo_ctrl.v12
1 files changed, 10 insertions, 2 deletions
diff --git a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
index 7219aa6a1..18119d2bd 100644
--- a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
+++ b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
@@ -19,6 +19,7 @@
module settings_readback_bus_fifo_ctrl
#(
+ parameter NUM_PERFS = 4,
parameter FIFO_DEPTH = 6, //64 entries depth
parameter PROT_DEST = 0 //protocol framer destination
)
@@ -29,6 +30,9 @@ module settings_readback_bus_fifo_ctrl
//current system time
input [63:0] vita_time,
+ //ready signals for multiple peripherals
+ input [NUM_PERFS-1:0] perfs_ready,
+
//input fifo36 interface control
input [35:0] in_data, input in_valid, output in_ready,
@@ -244,8 +248,12 @@ module settings_readback_bus_fifo_ctrl
`endif
//action occurs in the event state and when there is fifo space (should always be true)
- //the third condition is that is an event time has been set, action is delayed until that time
- wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && ((out_command_has_time)? (now || late || clear) : 1);
+ //the third condition is that all peripherals in the mask are ready/active high
+ //the fourth condition is that is an event time has been set, action is delayed until that time
+ wire [NUM_PERFS-1:0] perfs_mask = command_hdr_reg[10+NUM_PERFS-1:10];
+ wire perfs_in_mask_ready = (perfs_ready & perfs_mask) == perfs_mask;
+ wire time_ready = (out_command_has_time)? (now || late || clear) : 1;
+ wire action = (cmd_state == EVENT_CMD) && ~result_fifo_full && perfs_in_mask_ready && time_ready;
assign command_fifo_read = action;
assign result_fifo_write = action;