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author | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
commit | 8b377a9d6d0ad281474a8dbff49ea3b093178b28 (patch) | |
tree | 8e3c7a1b60f96df6e2140666d3b7afa5166d885d /usrp2/control_lib/clock_control_tb.v | |
parent | e92d36dcfe02afaedec348f2d8fc4523fb4e633b (diff) | |
download | uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.gz uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.bz2 uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.zip |
moved into subdir
Diffstat (limited to 'usrp2/control_lib/clock_control_tb.v')
-rw-r--r-- | usrp2/control_lib/clock_control_tb.v | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/usrp2/control_lib/clock_control_tb.v b/usrp2/control_lib/clock_control_tb.v new file mode 100644 index 000000000..4e705cf23 --- /dev/null +++ b/usrp2/control_lib/clock_control_tb.v @@ -0,0 +1,35 @@ + + +module clock_control_tb(); + + clock_control clock_control + (.reset(reset), + .aux_clk(aux_clk), + .clk_fpga(clk_fpga), + .clk_en(clk_en), + .clk_sel(clk_sel), + .clk_func(clk_func), + .clk_status(clk_status), + + .sen(sen), + .sclk(sclk), + .sdi(sdi), + .sdo(sdo) + ); + + reg reset, aux_clk; + + wire [1:0] clk_sel, clk_en; + + initial reset = 1'b1; + initial #1000 reset = 1'b0; + + initial aux_clk = 1'b0; + always #10 aux_clk = ~aux_clk; + + initial $dumpfile("clock_control_tb.vcd"); + initial $dumpvars(0,clock_control_tb); + + initial #10000 $finish; + +endmodule // clock_control_tb |