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author | Matt Ettus <matt@ettus.com> | 2011-07-19 11:40:11 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2011-07-19 13:49:28 -0700 |
commit | 7e085dae07589a6d8f926c8bcb8ae811f4debdd2 (patch) | |
tree | b4ec9a2d9f6243847c4618c83534d166d3ddb5f1 /usrp2/control_lib/atr_controller.v | |
parent | dbeea34b66c939c15eaaa0a9f805ee9286d0a878 (diff) | |
download | uhd-7e085dae07589a6d8f926c8bcb8ae811f4debdd2.tar.gz uhd-7e085dae07589a6d8f926c8bcb8ae811f4debdd2.tar.bz2 uhd-7e085dae07589a6d8f926c8bcb8ae811f4debdd2.zip |
appease the ISE gods
Diffstat (limited to 'usrp2/control_lib/atr_controller.v')
-rw-r--r-- | usrp2/control_lib/atr_controller.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v index 1f8d75d00..ee8b260c5 100644 --- a/usrp2/control_lib/atr_controller.v +++ b/usrp2/control_lib/atr_controller.v @@ -47,7 +47,7 @@ module atr_controller // Removing readback allows ram to be synthesized as LUTs instead of regs //always @(posedge clk_i) // dat_o <= atr_ram[adr_i[5:2]]; - always @* + always dat_o <= 32'd0; always @(posedge clk_i) |