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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:46:58 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:46:58 -0800 |
| commit | a170b9b42345794429486dd4f3316e84ea2cc871 (patch) | |
| tree | 2483dfa9eb239e3c2cec5701da6f2f5b5940d7ad /usrp1/toplevel/sizetest/sizetest.quartus | |
| parent | 320c70016f8798cb73c8d02eaa3728df48b5b3ab (diff) | |
| download | uhd-a170b9b42345794429486dd4f3316e84ea2cc871.tar.gz uhd-a170b9b42345794429486dd4f3316e84ea2cc871.tar.bz2 uhd-a170b9b42345794429486dd4f3316e84ea2cc871.zip | |
Moved usrp1 fpga files into usrp1 subdir.
Diffstat (limited to 'usrp1/toplevel/sizetest/sizetest.quartus')
| -rw-r--r-- | usrp1/toplevel/sizetest/sizetest.quartus | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/usrp1/toplevel/sizetest/sizetest.quartus b/usrp1/toplevel/sizetest/sizetest.quartus new file mode 100644 index 000000000..d1eaf227a --- /dev/null +++ b/usrp1/toplevel/sizetest/sizetest.quartus @@ -0,0 +1,19 @@ +COMPILER_SETTINGS_LIST +{ + COMPILER_SETTINGS = sizetest; +} +SIMULATOR_SETTINGS_LIST +{ + SIMULATOR_SETTINGS = sizetest; +} +SOFTWARE_SETTINGS_LIST +{ + SOFTWARE_SETTINGS = Debug; + SOFTWARE_SETTINGS = Release; +} +FILES +{ + VERILOG_FILE = ..\..\sdr_lib\cordic_stage.v; + VERILOG_FILE = ..\..\sdr_lib\cordic.v; + VERILOG_FILE = sizetest.v; +} |