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| author | Josh Blum <josh@joshknows.com> | 2011-09-14 21:54:08 -0400 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-09-28 13:19:35 -0700 |
| commit | 24b07e1b0dbe8ab9d72c46f65c14c34e84347554 (patch) | |
| tree | 4c8e99d2ed6f79a63b8a7969dea8a1377ed99942 /usrp1/sdr_lib | |
| parent | a08af5a91e45fcb721d9aca54cdc05673e8d63e2 (diff) | |
| download | uhd-24b07e1b0dbe8ab9d72c46f65c14c34e84347554.tar.gz uhd-24b07e1b0dbe8ab9d72c46f65c14c34e84347554.tar.bz2 uhd-24b07e1b0dbe8ab9d72c46f65c14c34e84347554.zip | |
usrp1: copy regs files into common and fix include paths
Diffstat (limited to 'usrp1/sdr_lib')
| -rw-r--r-- | usrp1/sdr_lib/adc_interface.v | 4 | ||||
| -rw-r--r-- | usrp1/sdr_lib/io_pins.v | 4 | ||||
| -rw-r--r-- | usrp1/sdr_lib/master_control_multi.v | 4 | ||||
| -rw-r--r-- | usrp1/sdr_lib/rx_buffer.v | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/usrp1/sdr_lib/adc_interface.v b/usrp1/sdr_lib/adc_interface.v index f18ffc104..cb78f332a 100644 --- a/usrp1/sdr_lib/adc_interface.v +++ b/usrp1/sdr_lib/adc_interface.v @@ -1,7 +1,7 @@ -`include "../../firmware/include/fpga_regs_common.v" -`include "../../firmware/include/fpga_regs_standard.v" +`include "../common/fpga_regs_common.v" +`include "../common/fpga_regs_standard.v" module adc_interface (input clock, input reset, input enable, diff --git a/usrp1/sdr_lib/io_pins.v b/usrp1/sdr_lib/io_pins.v index ad1b7b4a8..b8bf59555 100644 --- a/usrp1/sdr_lib/io_pins.v +++ b/usrp1/sdr_lib/io_pins.v @@ -19,8 +19,8 @@ // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // -`include "../../firmware/include/fpga_regs_common.v" -`include "../../firmware/include/fpga_regs_standard.v" +`include "../common/fpga_regs_common.v" +`include "../common/fpga_regs_standard.v" module io_pins ( inout wire [15:0] io_0, inout wire [15:0] io_1, inout wire [15:0] io_2, inout wire [15:0] io_3, diff --git a/usrp1/sdr_lib/master_control_multi.v b/usrp1/sdr_lib/master_control_multi.v index cab96a79f..eee8ebfa3 100644 --- a/usrp1/sdr_lib/master_control_multi.v +++ b/usrp1/sdr_lib/master_control_multi.v @@ -19,8 +19,8 @@ // Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA // `include "config.vh" -`include "../../../firmware/include/fpga_regs_common.v" -`include "../../../firmware/include/fpga_regs_standard.v" +`include "../../common/fpga_regs_common.v" +`include "../../common/fpga_regs_standard.v" // Clock, enable, and reset controls for whole system // Modified version to enable multi_usrp synchronisation diff --git a/usrp1/sdr_lib/rx_buffer.v b/usrp1/sdr_lib/rx_buffer.v index d17294b98..5541d2912 100644 --- a/usrp1/sdr_lib/rx_buffer.v +++ b/usrp1/sdr_lib/rx_buffer.v @@ -22,8 +22,8 @@ // Interface to Cypress FX2 bus // A packet is 512 Bytes, the fifo has 4096 lines of 18 bits each -`include "../../firmware/include/fpga_regs_common.v" -`include "../../firmware/include/fpga_regs_standard.v" +`include "../common/fpga_regs_common.v" +`include "../common/fpga_regs_standard.v" module rx_buffer ( // Read/USB side |