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author | Matt Ettus <matt@ettus.com> | 2010-03-25 17:35:05 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-03-25 17:35:05 -0700 |
commit | 16818dc98e97b69a028c47e66ebfb16e32565533 (patch) | |
tree | 011ff2bcc793d8b38d0fe34adc1bccceb6ab81b8 /usrp1/sdr_lib/setting_reg_masked.v | |
parent | fdb6175aef0aa1896c6319d5425955ce0a5dc86b (diff) | |
parent | 904b35c689d38694913606c569a9d324533ff765 (diff) | |
download | uhd-16818dc98e97b69a028c47e66ebfb16e32565533.tar.gz uhd-16818dc98e97b69a028c47e66ebfb16e32565533.tar.bz2 uhd-16818dc98e97b69a028c47e66ebfb16e32565533.zip |
Merge branch 'master' into udp
Diffstat (limited to 'usrp1/sdr_lib/setting_reg_masked.v')
-rw-r--r-- | usrp1/sdr_lib/setting_reg_masked.v | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/usrp1/sdr_lib/setting_reg_masked.v b/usrp1/sdr_lib/setting_reg_masked.v new file mode 100644 index 000000000..72f7e21eb --- /dev/null +++ b/usrp1/sdr_lib/setting_reg_masked.v @@ -0,0 +1,26 @@ + + +module setting_reg_masked + ( input clock, input reset, input strobe, input wire [6:0] addr, + input wire [31:0] in, output reg [31:0] out, output reg changed); +/* upper 16 bits are mask, lower 16 bits are value + * Note that you get a 16 bit register, not a 32 bit one */ + + parameter my_addr = 0; + + always @(posedge clock) + if(reset) + begin + out <= #1 32'd0; + changed <= #1 1'b0; + end + else + if(strobe & (my_addr==addr)) + begin + out <= #1 (out & ~in[31:16]) | (in[15:0] & in[31:16] ); + changed <= #1 1'b1; + end + else + changed <= #1 1'b0; + +endmodule // setting_reg_masked |