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authorMatt Ettus <matt@ettus.com>2010-03-25 17:35:05 -0700
committerMatt Ettus <matt@ettus.com>2010-03-25 17:35:05 -0700
commit16818dc98e97b69a028c47e66ebfb16e32565533 (patch)
tree011ff2bcc793d8b38d0fe34adc1bccceb6ab81b8 /usrp1/sdr_lib/setting_reg.v
parentfdb6175aef0aa1896c6319d5425955ce0a5dc86b (diff)
parent904b35c689d38694913606c569a9d324533ff765 (diff)
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Merge branch 'master' into udp
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-rw-r--r--usrp1/sdr_lib/setting_reg.v23
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diff --git a/usrp1/sdr_lib/setting_reg.v b/usrp1/sdr_lib/setting_reg.v
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+
+
+module setting_reg
+ ( input clock, input reset, input strobe, input wire [6:0] addr,
+ input wire [31:0] in, output reg [31:0] out, output reg changed);
+ parameter my_addr = 0;
+
+ always @(posedge clock)
+ if(reset)
+ begin
+ out <= #1 32'd0;
+ changed <= #1 1'b0;
+ end
+ else
+ if(strobe & (my_addr==addr))
+ begin
+ out <= #1 in;
+ changed <= #1 1'b1;
+ end
+ else
+ changed <= #1 1'b0;
+
+endmodule // setting_reg