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author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:46:58 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:46:58 -0800 |
commit | a170b9b42345794429486dd4f3316e84ea2cc871 (patch) | |
tree | 2483dfa9eb239e3c2cec5701da6f2f5b5940d7ad /usrp1/sdr_lib/hb/ram32_2sum.v | |
parent | 320c70016f8798cb73c8d02eaa3728df48b5b3ab (diff) | |
download | uhd-a170b9b42345794429486dd4f3316e84ea2cc871.tar.gz uhd-a170b9b42345794429486dd4f3316e84ea2cc871.tar.bz2 uhd-a170b9b42345794429486dd4f3316e84ea2cc871.zip |
Moved usrp1 fpga files into usrp1 subdir.
Diffstat (limited to 'usrp1/sdr_lib/hb/ram32_2sum.v')
-rw-r--r-- | usrp1/sdr_lib/hb/ram32_2sum.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/usrp1/sdr_lib/hb/ram32_2sum.v b/usrp1/sdr_lib/hb/ram32_2sum.v new file mode 100644 index 000000000..d1f55b7d0 --- /dev/null +++ b/usrp1/sdr_lib/hb/ram32_2sum.v @@ -0,0 +1,22 @@ + + +module ram32_2sum (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr1, input [4:0] rd_addr2, + output reg [15:0] sum); + + reg [15:0] ram_array [0:31]; + wire [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + + +endmodule // ram32_2sum + |