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author | Matt Ettus <matt@ettus.com> | 2010-03-25 17:35:05 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-03-25 17:35:05 -0700 |
commit | 16818dc98e97b69a028c47e66ebfb16e32565533 (patch) | |
tree | 011ff2bcc793d8b38d0fe34adc1bccceb6ab81b8 /usrp1/sdr_lib/hb/ram32_2sum.v | |
parent | fdb6175aef0aa1896c6319d5425955ce0a5dc86b (diff) | |
parent | 904b35c689d38694913606c569a9d324533ff765 (diff) | |
download | uhd-16818dc98e97b69a028c47e66ebfb16e32565533.tar.gz uhd-16818dc98e97b69a028c47e66ebfb16e32565533.tar.bz2 uhd-16818dc98e97b69a028c47e66ebfb16e32565533.zip |
Merge branch 'master' into udp
Diffstat (limited to 'usrp1/sdr_lib/hb/ram32_2sum.v')
-rw-r--r-- | usrp1/sdr_lib/hb/ram32_2sum.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/usrp1/sdr_lib/hb/ram32_2sum.v b/usrp1/sdr_lib/hb/ram32_2sum.v new file mode 100644 index 000000000..d1f55b7d0 --- /dev/null +++ b/usrp1/sdr_lib/hb/ram32_2sum.v @@ -0,0 +1,22 @@ + + +module ram32_2sum (input clock, input write, + input [4:0] wr_addr, input [15:0] wr_data, + input [4:0] rd_addr1, input [4:0] rd_addr2, + output reg [15:0] sum); + + reg [15:0] ram_array [0:31]; + wire [16:0] sum_int; + + always @(posedge clock) + if(write) + ram_array[wr_addr] <= #1 wr_data; + + assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2]; + + always @(posedge clock) + sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]); + + +endmodule // ram32_2sum + |