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authorMatt Ettus <matt@ettus.com>2010-03-25 17:35:05 -0700
committerMatt Ettus <matt@ettus.com>2010-03-25 17:35:05 -0700
commit16818dc98e97b69a028c47e66ebfb16e32565533 (patch)
tree011ff2bcc793d8b38d0fe34adc1bccceb6ab81b8 /usrp1/sdr_lib/gen_sync.v
parentfdb6175aef0aa1896c6319d5425955ce0a5dc86b (diff)
parent904b35c689d38694913606c569a9d324533ff765 (diff)
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Merge branch 'master' into udp
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diff --git a/usrp1/sdr_lib/gen_sync.v b/usrp1/sdr_lib/gen_sync.v
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+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+module gen_sync
+ ( input clock,
+ input reset,
+ input enable,
+ input [7:0] rate,
+ output wire sync );
+
+// parameter width = 8;
+
+ reg [7:0] counter;
+ assign sync = |(((rate+1)>>1)& counter);
+
+ always @(posedge clock)
+ if(reset || ~enable)
+ counter <= #1 0;
+ else if(counter == rate)
+ counter <= #1 0;
+ else
+ counter <= #1 counter + 8'd1;
+
+endmodule // gen_sync
+