Moved usrp1 fpga files into usrp1 subdir.

1 files changed, 33 insertions, 0 deletions

diff --git a/usrp1/megacells/addsub16.cmp b/usrp1/megacells/addsub16.cmp
new file mode 100755
index 000000000..e32e01b31
--- /dev/null
+++ b/usrp1/megacells/addsub16.cmp
@@ -0,0 +1,33 @@
+--Copyright (C) 1991-2003 Altera Corporation
+--Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
+--support information,  device programming or simulation file,  and any other
+--associated  documentation or information  provided by  Altera  or a partner
+--under  Altera's   Megafunction   Partnership   Program  may  be  used  only
+--to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
+--other  use  of such  megafunction  design,  netlist,  support  information,
+--device programming or simulation file,  or any other  related documentation
+--or information  is prohibited  for  any  other purpose,  including, but not
+--limited to  modification,  reverse engineering,  de-compiling, or use  with
+--any other  silicon devices,  unless such use is  explicitly  licensed under
+--a separate agreement with  Altera  or a megafunction partner.  Title to the
+--intellectual property,  including patents,  copyrights,  trademarks,  trade
+--secrets,  or maskworks,  embodied in any such megafunction design, netlist,
+--support  information,  device programming or simulation file,  or any other
+--related documentation or information provided by  Altera  or a megafunction
+--partner, remains with Altera, the megafunction partner, or their respective
+--licensors. No other licenses, including any licenses needed under any third
+--party's intellectual property, are provided herein.
+
+
+component addsub16
+	PORT
+	(
+		add_sub		: IN STD_LOGIC ;
+		dataa		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		datab		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		aclr		: IN STD_LOGIC ;
+		clken		: IN STD_LOGIC ;
+		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
+	);
+end component;