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authoreb <eb@221aa14e-8319-0410-a670-987f0aec2ac5>2007-03-03 03:49:04 +0000
committereb <eb@221aa14e-8319-0410-a670-987f0aec2ac5>2007-03-03 03:49:04 +0000
commit78ba89f589ac3a1e53e2767edd8811d231e13946 (patch)
tree1e4fcf5c5d66da312d84948d2896475f378634c1 /toplevel
parenta344417b9510e111f9b37b09c83545f08b0123c1 (diff)
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updated qsf file to Quartus 6.1. No semantic changes
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4694 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'toplevel')
-rw-r--r--toplevel/usrp_std/usrp_std.qsf22
1 files changed, 11 insertions, 11 deletions
diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf
index 8297f0f7b..fe6773f67 100644
--- a/toplevel/usrp_std/usrp_std.qsf
+++ b/toplevel/usrp_std/usrp_std.qsf
@@ -223,7 +223,7 @@ set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TOP_LEVEL_ENTITY usrp_std
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
-set_global_assignment -name AUTO_ENABLE_SMART_COMPILE On
+set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
# Fitter Assignments
# ==================
@@ -314,7 +314,7 @@ set_global_assignment -name HCPY_VREF_PINS OFF
# ========================
set_global_assignment -name HUB_ENTITY_NAME SLD_HUB
set_global_assignment -name HUB_INSTANCE_NAME SLD_HUB_INST
-set_global_assignment -name ENABLE_SIGNALTAP Off
+set_global_assignment -name ENABLE_SIGNALTAP OFF
# LogicLock Region Assignments
# ============================
@@ -326,8 +326,8 @@ set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
# Timing Assignments
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
- set_global_assignment -name FMAX_REQUIREMENT "1.0 MHz" -section_id SCLK
- set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
+set_global_assignment -name FMAX_REQUIREMENT "1 MHz" -section_id SCLK
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id SCLK
# end CLOCK(SCLK)
# ---------------
@@ -338,8 +338,8 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id SCLK
# Timing Assignments
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
- set_global_assignment -name FMAX_REQUIREMENT "64.0 MHz" -section_id master_clk
- set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
+set_global_assignment -name FMAX_REQUIREMENT "64 MHz" -section_id master_clk
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id master_clk
# end CLOCK(master_clk)
# ---------------------
@@ -350,8 +350,8 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id master_clk
# Timing Assignments
# ==================
set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
- set_global_assignment -name FMAX_REQUIREMENT "48.0 MHz" -section_id usbclk
- set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
+set_global_assignment -name FMAX_REQUIREMENT "48 MHz" -section_id usbclk
+set_global_assignment -name INCLUDE_EXTERNAL_PIN_DELAYS_IN_FMAX_CALCULATIONS OFF -section_id usbclk
# end CLOCK(usbclk)
# -----------------
@@ -361,9 +361,9 @@ set_global_assignment -name DUTY_CYCLE 50 -section_id usbclk
# Timing Assignments
# ==================
- set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
- set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
- set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
+set_instance_assignment -name CLOCK_SETTINGS SCLK -to SCLK
+set_instance_assignment -name CLOCK_SETTINGS usbclk -to usbclk
+set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk
# end ENTITY(usrp_std)
# --------------------