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| author | eb <eb@221aa14e-8319-0410-a670-987f0aec2ac5> | 2007-03-05 05:00:02 +0000 |
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| committer | eb <eb@221aa14e-8319-0410-a670-987f0aec2ac5> | 2007-03-05 05:00:02 +0000 |
| commit | a67127dcd59dd7f7d58323f05ed8504faafe8c63 (patch) | |
| tree | a7de20164cf9e33788f8644f6edae8584e2f7005 /toplevel/usrp_std/usrp_std.qsf | |
| parent | 2a732b0122279fc795203e176c430d6f9974c66d (diff) | |
| download | uhd-a67127dcd59dd7f7d58323f05ed8504faafe8c63.tar.gz uhd-a67127dcd59dd7f7d58323f05ed8504faafe8c63.tar.bz2 uhd-a67127dcd59dd7f7d58323f05ed8504faafe8c63.zip | |
Refactored FPGA *.vh files. Moved common pieces to toplevel/include.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@4713 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'toplevel/usrp_std/usrp_std.qsf')
| -rw-r--r-- | toplevel/usrp_std/usrp_std.qsf | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/toplevel/usrp_std/usrp_std.qsf b/toplevel/usrp_std/usrp_std.qsf index fe6773f67..e43d39ba3 100644 --- a/toplevel/usrp_std/usrp_std.qsf +++ b/toplevel/usrp_std/usrp_std.qsf @@ -370,7 +370,6 @@ set_instance_assignment -name CLOCK_SETTINGS master_clk -to master_clk set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v -set_global_assignment -name VERILOG_FILE usrp_std.vh set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v |