Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5

1 files changed, 341 insertions, 0 deletions

diff --git a/top/u2_fpga/u2_fpga.ucf b/top/u2_fpga/u2_fpga.ucf
new file mode 100755
index 000000000..5d2124819
--- /dev/null
+++ b/top/u2_fpga/u2_fpga.ucf
@@ -0,0 +1,341 @@
+NET "adc_a[0]"  LOC = "A14"  ;
+NET "adc_a[10]"  LOC = "D20"  ;
+NET "adc_a[11]"  LOC = "D19"  ;
+NET "adc_a[12]"  LOC = "D21"  ;
+NET "adc_a[13]"  LOC = "E18"  ;
+NET "adc_a[1]"  LOC = "B14"  ;
+NET "adc_a[2]"  LOC = "C13"  ;
+NET "adc_a[3]"  LOC = "D13"  ;
+NET "adc_a[4]"  LOC = "A13"  ;
+NET "adc_a[5]"  LOC = "B13"  ;
+NET "adc_a[6]"  LOC = "E12"  ;
+NET "adc_a[7]"  LOC = "C22"  ;
+NET "adc_a[8]"  LOC = "C20"  ;
+NET "adc_a[9]"  LOC = "C21"  ;
+NET "adc_b[0]"  LOC = "A12"  ;
+NET "adc_b[10]"  LOC = "D18"  ;
+NET "adc_b[11]"  LOC = "B18"  ;
+NET "adc_b[12]"  LOC = "D17"  ;
+NET "adc_b[13]"  LOC = "E17"  ;
+NET "adc_b[1]"  LOC = "E16"  ;
+NET "adc_b[2]"  LOC = "F12"  ;
+NET "adc_b[3]"  LOC = "F13"  ;
+NET "adc_b[4]"  LOC = "F16"  ;
+NET "adc_b[5]"  LOC = "F17"  ;
+NET "adc_b[6]"  LOC = "C19"  ;
+NET "adc_b[7]"  LOC = "B20"  ;
+NET "adc_b[8]"  LOC = "B19"  ;
+NET "adc_b[9]"  LOC = "C18"  ;
+NET "clk_en[0]"  LOC = "C4"  ;
+NET "clk_en[1]"  LOC = "D1"  ;
+NET "clk_sel[0]"  LOC = "C3"  ;
+NET "clk_sel[1]"  LOC = "C2"  ;
+NET "dac_a[0]"  LOC = "A5"  ;
+NET "dac_a[10]"  LOC = "L2"  ;
+NET "dac_a[11]"  LOC = "L4"  ;
+NET "dac_a[12]"  LOC = "L3"  ;
+NET "dac_a[13]"  LOC = "L6"  ;
+NET "dac_a[14]"  LOC = "L5"  ;
+NET "dac_a[15]"  LOC = "K2"  ;
+NET "dac_a[1]"  LOC = "B5"  ;
+NET "dac_a[2]"  LOC = "C5"  ;
+NET "dac_a[3]"  LOC = "D5"  ;
+NET "dac_a[4]"  LOC = "A4"  ;
+NET "dac_a[5]"  LOC = "B4"  ;
+NET "dac_a[6]"  LOC = "F6"  ;
+NET "dac_a[7]"  LOC = "D10"  ;
+NET "dac_a[8]"  LOC = "D9"  ;
+NET "dac_a[9]"  LOC = "A10"  ;
+NET "dac_b[0]"  LOC = "D11"  ;
+NET "dac_b[10]"  LOC = "F9"  ;
+NET "dac_b[11]"  LOC = "A8"  ;
+NET "dac_b[12]"  LOC = "B8"  ;
+NET "dac_b[13]"  LOC = "D7"  ;
+NET "dac_b[14]"  LOC = "E7"  ;
+NET "dac_b[15]"  LOC = "B6"  ;
+NET "dac_b[1]"  LOC = "E11"  ;
+NET "dac_b[2]"  LOC = "F11"  ;
+NET "dac_b[3]"  LOC = "B10"  ;
+NET "dac_b[4]"  LOC = "C10"  ;
+NET "dac_b[5]"  LOC = "E10"  ;
+NET "dac_b[6]"  LOC = "F10"  ;
+NET "dac_b[7]"  LOC = "A9"  ;
+NET "dac_b[8]"  LOC = "B9"  ;
+NET "dac_b[9]"  LOC = "E9"  ;
+NET "debug[0]"  LOC = "N5"  ;
+NET "debug[10]"  LOC = "R4"  ;
+NET "debug[11]"  LOC = "T3"  ;
+NET "debug[12]"  LOC = "U3"  ;
+NET "debug[13]"  LOC = "M2"  ;
+NET "debug[14]"  LOC = "M3"  ;
+NET "debug[15]"  LOC = "M4"  ;
+NET "debug[16]"  LOC = "M5"  ;
+NET "debug[17]"  LOC = "M6"  ;
+NET "debug[18]"  LOC = "N1"  ;
+NET "debug[19]"  LOC = "N2"  ;
+NET "debug[1]"  LOC = "N6"  ;
+NET "debug[20]"  LOC = "N3"  ;
+NET "debug[21]"  LOC = "T1"  ;
+NET "debug[22]"  LOC = "T2"  ;
+NET "debug[23]"  LOC = "U2"  ;
+NET "debug[24]"  LOC = "T4"  ;
+NET "debug[25]"  LOC = "U4"  ;
+NET "debug[26]"  LOC = "T5"  ;
+NET "debug[27]"  LOC = "T6"  ;
+NET "debug[28]"  LOC = "U5"  ;
+NET "debug[29]"  LOC = "V5"  ;
+NET "debug[2]"  LOC = "P1"  ;
+NET "debug[30]"  LOC = "W2"  ;
+NET "debug[31]"  LOC = "W3"  ;
+NET "debug[3]"  LOC = "P2"  ;
+NET "debug[4]"  LOC = "P4"  ;
+NET "debug[5]"  LOC = "P5"  ;
+NET "debug[6]"  LOC = "R1"  ;
+NET "debug[7]"  LOC = "R2"  ;
+NET "debug[8]"  LOC = "P6"  ;
+NET "debug[9]"  LOC = "R5"  ;
+NET "debug_clk[0]"  LOC = "N4"  ;
+NET "debug_clk[1]"  LOC = "M1"  ;
+NET "GMII_RXD[0]"  LOC = "AA15"  ;
+NET "GMII_RXD[1]"  LOC = "AB15"  ;
+NET "GMII_RXD[2]"  LOC = "U14"  ;
+NET "GMII_RXD[3]"  LOC = "V14"  ;
+NET "GMII_RXD[4]"  LOC = "U13"  ;
+NET "GMII_RXD[5]"  LOC = "V13"  ;
+NET "GMII_RXD[6]"  LOC = "Y13"  ;
+NET "GMII_RXD[7]"  LOC = "AA13"  ;
+NET "GMII_TXD[0]"  LOC = "W14"  ;
+NET "GMII_TXD[1]"  LOC = "AA20"  ;
+NET "GMII_TXD[2]"  LOC = "AB20"  ;
+NET "GMII_TXD[3]"  LOC = "Y18"  ;
+NET "GMII_TXD[4]"  LOC = "AA18"  ;
+NET "GMII_TXD[5]"  LOC = "AB18"  ;
+NET "GMII_TXD[6]"  LOC = "V17"  ;
+NET "GMII_TXD[7]"  LOC = "W17"  ;
+NET "io_rx[0]"  LOC = "L21"  ;
+NET "io_rx[10]"  LOC = "F21"  ;
+NET "io_rx[11]"  LOC = "F20"  ;
+NET "io_rx[12]"  LOC = "G19"  ;
+NET "io_rx[13]"  LOC = "G18"  ;
+NET "io_rx[14]"  LOC = "G17"  ;
+NET "io_rx[15]"  LOC = "E22"  ;
+NET "io_rx[1]"  LOC = "L20"  ;
+NET "io_rx[2]"  LOC = "L19"  ;
+NET "io_rx[3]"  LOC = "L18"  ;
+NET "io_rx[4]"  LOC = "L17"  ;
+NET "io_rx[5]"  LOC = "K22"  ;
+NET "io_rx[6]"  LOC = "K21"  ;
+NET "io_rx[7]"  LOC = "K20"  ;
+NET "io_rx[8]"  LOC = "G22"  ;
+NET "io_rx[9]"  LOC = "G21"  ;
+NET "io_tx[0]"  LOC = "K4"  ;
+NET "io_tx[10]"  LOC = "E1"  ;
+NET "io_tx[11]"  LOC = "E3"  ;
+NET "io_tx[12]"  LOC = "F4"  ;
+NET "io_tx[13]"  LOC = "D2"  ;
+NET "io_tx[14]"  LOC = "D4"  ;
+NET "io_tx[15]"  LOC = "E4"  ;
+NET "io_tx[1]"  LOC = "K3"  ;
+NET "io_tx[2]"  LOC = "G1"  ;
+NET "io_tx[3]"  LOC = "G5"  ;
+NET "io_tx[4]"  LOC = "H5"  ;
+NET "io_tx[5]"  LOC = "F3"  ;
+NET "io_tx[6]"  LOC = "F2"  ;
+NET "io_tx[7]"  LOC = "F5"  ;
+NET "io_tx[8]"  LOC = "G6"  ;
+NET "io_tx[9]"  LOC = "E2"  ;
+NET "RAM_A[0]"  LOC = "N22"  ;
+NET "RAM_A[10]"  LOC = "P18"  ;
+NET "RAM_A[11]"  LOC = "R19"  ;
+NET "RAM_A[12]"  LOC = "P19"  ;
+NET "RAM_A[13]"  LOC = "R21"  ;
+NET "RAM_A[14]"  LOC = "R22"  ;
+NET "RAM_A[15]"  LOC = "T19"  ;
+NET "RAM_A[16]"  LOC = "T20"  ;
+NET "RAM_A[17]"  LOC = "U20"  ;
+NET "RAM_A[18]"  LOC = "W19"  ;
+NET "RAM_A[1]"  LOC = "N20"  ;
+NET "RAM_A[2]"  LOC = "T21"  ;
+NET "RAM_A[3]"  LOC = "M22"  ;
+NET "RAM_A[4]"  LOC = "N19"  ;
+NET "RAM_A[5]"  LOC = "N17"  ;
+NET "RAM_A[6]"  LOC = "N18"  ;
+NET "RAM_A[7]"  LOC = "P21"  ;
+NET "RAM_A[8]"  LOC = "P22"  ;
+NET "RAM_A[9]"  LOC = "P17"  ;
+NET "RAM_D[0]"  LOC = "Y21"  ;
+NET "RAM_D[10]"  LOC = "V22"  ;
+NET "RAM_D[11]"  LOC = "V21"  ;
+NET "RAM_D[12]"  LOC = "T17"  ;
+NET "RAM_D[13]"  LOC = "U18"  ;
+NET "RAM_D[14]"  LOC = "U21"  ;
+NET "RAM_D[15]"  LOC = "R18"  ;
+NET "RAM_D[16]"  LOC = "T18"  ;
+NET "RAM_D[17]"  LOC = "T22"  ;
+NET "RAM_D[1]"  LOC = "Y20"  ;
+NET "RAM_D[2]"  LOC = "Y19"  ;
+NET "RAM_D[3]"  LOC = "W22"  ;
+NET "RAM_D[4]"  LOC = "Y22"  ;
+NET "RAM_D[5]"  LOC = "V19"  ;
+NET "RAM_D[6]"  LOC = "W21"  ;
+NET "RAM_D[7]"  LOC = "W20"  ;
+NET "RAM_D[8]"  LOC = "U19"  ;
+NET "RAM_D[9]"  LOC = "V20"  ;
+NET "ser_r[0]"  LOC = "AB10"  ;
+NET "ser_r[10]"  LOC = "W10"  ;
+NET "ser_r[11]"  LOC = "Y1"  ;
+NET "ser_r[12]"  LOC = "Y3"  ;
+NET "ser_r[13]"  LOC = "Y2"  ;
+NET "ser_r[14]"  LOC = "W4"  ;
+NET "ser_r[15]"  LOC = "W1"  ;
+NET "ser_r[1]"  LOC = "AA10"  ;
+NET "ser_r[2]"  LOC = "U9"  ;
+NET "ser_r[3]"  LOC = "U6"  ;
+NET "ser_r[4]"  LOC = "AB11"  ;
+NET "ser_r[5]"  LOC = "Y7"  ;
+NET "ser_r[6]"  LOC = "W7"  ;
+NET "ser_r[7]"  LOC = "AB7"  ;
+NET "ser_r[8]"  LOC = "AA7"  ;
+NET "ser_r[9]"  LOC = "W9"  ;
+NET "ser_t[0]"  LOC = "V7"  ;
+NET "ser_t[10]"  LOC = "AA6"  ;
+NET "ser_t[11]"  LOC = "Y6"  ;
+NET "ser_t[12]"  LOC = "W8"  ;
+NET "ser_t[13]"  LOC = "V8"  ;
+NET "ser_t[14]"  LOC = "AB8"  ;
+NET "ser_t[15]"  LOC = "AA8"  ;
+NET "ser_t[1]"  LOC = "V10"  ;
+NET "ser_t[2]"  LOC = "AB4"  ;
+NET "ser_t[3]"  LOC = "AA4"  ;
+NET "ser_t[4]"  LOC = "Y5"  ;
+NET "ser_t[5]"  LOC = "W5"  ;
+NET "ser_t[6]"  LOC = "AB5"  ;
+NET "ser_t[7]"  LOC = "AA5"  ;
+NET "ser_t[8]"  LOC = "W6"  ;
+NET "ser_t[9]"  LOC = "V6"  ;
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_oen_a"  LOC = "E19"  ; 
+NET "adc_oen_b"  LOC = "C17"  ; 
+NET "adc_ovf_a"  LOC = "F18"  ; 
+NET "adc_ovf_b"  LOC = "B17"  ; 
+NET "adc_pdn_a"  LOC = "E20"  ; 
+NET "adc_pdn_b"  LOC = "D15"  ; 
+NET "clk_fpga_n"  LOC = "B11"  ; 
+NET "clk_fpga_p"  LOC = "A11"  ; 
+NET "clk_func"  LOC = "C12"  ; 
+NET "clk_status"  LOC = "B12"  ; 
+NET "clk_to_mac"  LOC = "AB12"  ; 
+NET "cpld_clk"  LOC = "AB14"  ; 
+NET "cpld_din"  LOC = "AA14"  ; 
+NET "cpld_done"  LOC = "V12"  ; 
+NET "cpld_mode"  LOC = "U12"  ; 
+NET "cpld_start"  LOC = "AA9"  ; 
+NET "exp_pps_in_n"  LOC = "V4"  ; 
+NET "exp_pps_in_p"  LOC = "V3"  ; 
+NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "exp_pps_out_p"  LOC = "V1"  ; 
+NET "GMII_COL"  LOC = "U16"  ; 
+NET "GMII_CRS"  LOC = "U17"  ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_RX_CLK"  LOC = "W16"  ; 
+NET "GMII_RX_DV"  LOC = "AB16"  ; 
+NET "GMII_RX_ER"  LOC = "AA16"  ; 
+NET "GMII_TX_CLK"  LOC = "W13"  ; 
+NET "GMII_TX_EN"  LOC = "Y17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "led1"  LOC = "V11"  ; 
+NET "led2"  LOC = "Y12"  ; 
+NET "MDC"  LOC = "V18"  ; 
+NET "MDIO"  LOC = "Y16" | PULLUP ; 
+NET "PHY_CLK"  LOC = "V15"  ; 
+NET "PHY_INTn"  LOC = "AB13"  ; 
+NET "PHY_RESETn"  LOC = "AA19"  ; 
+NET "pps_in"  LOC = "Y11"  ; 
+NET "RAM_CE1n"  LOC = "N21"  ; 
+NET "RAM_CENn"  LOC = "M18"  ; 
+NET "RAM_CLK"  LOC = "M17"  ; 
+NET "RAM_LDn"  LOC = "M21"  ; 
+NET "RAM_OEn"  LOC = "M19"  ; 
+NET "RAM_WEn"  LOC = "M20"  ; 
+NET "SCL"  LOC = "A7"  ; 
+NET "SCL_force"  LOC = "E8"  ; 
+NET "sclk"  LOC = "K5"  ; 
+NET "sclk_rx_adc"  LOC = "J17"  ; 
+NET "sclk_rx_dac"  LOC = "J19"  ; 
+NET "sclk_rx_db"  LOC = "F19"  ; 
+NET "sclk_tx_adc"  LOC = "H1"  ; 
+NET "sclk_tx_dac"  LOC = "J5"  ; 
+NET "sclk_tx_db"  LOC = "D3"  ; 
+NET "SDA"  LOC = "D8"  ; 
+NET "SDA_force"  LOC = "C11"  ; 
+NET "sdi"  LOC = "J1"  ; 
+NET "sdi_rx_adc"  LOC = "H22"  ; 
+NET "sdi_rx_dac"  LOC = "J21"  ; 
+NET "sdi_rx_db"  LOC = "H19"  ; 
+NET "sdi_tx_adc"  LOC = "J4"  ; 
+NET "sdi_tx_dac"  LOC = "J6"  ; 
+NET "sdi_tx_db"  LOC = "G4"  ; 
+NET "sdo"  LOC = "J2"  ; 
+NET "sdo_rx_adc"  LOC = "H21"  ; 
+NET "sdo_rx_db"  LOC = "G20"  ; 
+NET "sdo_tx_adc"  LOC = "H2"  ; 
+NET "sdo_tx_db"  LOC = "G3"  ; 
+NET "sen_clk"  LOC = "K6"  ; 
+NET "sen_dac"  LOC = "L1"  ; 
+NET "sen_rx_adc"  LOC = "H18"  ; 
+NET "sen_rx_dac"  LOC = "J18"  ; 
+NET "sen_rx_db"  LOC = "D22"  ; 
+NET "sen_tx_adc"  LOC = "G2"  ; 
+NET "sen_tx_dac"  LOC = "H4"  ; 
+NET "sen_tx_db"  LOC = "C1"  ; 
+NET "ser_enable"  LOC = "W11"  ; 
+NET "ser_loopen"  LOC = "Y4"  ; 
+NET "ser_prbsen"  LOC = "AA3"  ; 
+NET "ser_rklsb"  LOC = "V9"  ; 
+NET "ser_rkmsb"  LOC = "Y10"  ; 
+NET "ser_rx_clk"  LOC = "AA11"  ; 
+NET "ser_rx_en"  LOC = "AB9"  ; 
+NET "ser_tklsb"  LOC = "U10" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_tkmsb"  LOC = "U11" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_tx_clk"  LOC = "U7" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_t<0>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<1>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<2>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<3>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<4>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<5>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<6>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<7>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<8>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<9>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<10>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<11>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<12>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<13>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<14>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<15>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE