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| author | Matt Ettus <matt@ettus.com> | 2009-09-01 23:19:15 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-09-01 23:19:15 -0700 |
| commit | e784f7bc57ca414d2aadbc69e855c061d0af7d1f (patch) | |
| tree | 16ef06b8e06ae22ef0150e9d5f2fd60d7523b045 /simple_gemac | |
| parent | 91636cbac2b3edfba45321f1050d0b90b34ab696 (diff) | |
| download | uhd-e784f7bc57ca414d2aadbc69e855c061d0af7d1f.tar.gz uhd-e784f7bc57ca414d2aadbc69e855c061d0af7d1f.tar.bz2 uhd-e784f7bc57ca414d2aadbc69e855c061d0af7d1f.zip | |
fixed addressing of registers, and added write enables to those that were missing. MDIO seems ok.
Diffstat (limited to 'simple_gemac')
| -rw-r--r-- | simple_gemac/simple_gemac_wb.v | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/simple_gemac/simple_gemac_wb.v b/simple_gemac/simple_gemac_wb.v index ca7d4a3fc..cc2cdf7ec 100644 --- a/simple_gemac/simple_gemac_wb.v +++ b/simple_gemac/simple_gemac_wb.v @@ -79,20 +79,23 @@ module simple_gemac_wb wire [2:0] MIISTATUS; wb_reg #(.ADDR(5),.DEFAULT(0)) - wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) ); + wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) ); wb_reg #(.ADDR(6),.DEFAULT(0)) - wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .dat_i(wb_dat_i), .dat_o(MIIADDRESS) ); + wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(MIIADDRESS) ); wb_reg #(.ADDR(7),.DEFAULT(0)) - wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .dat_i(wb_dat_i), .dat_o(CtrlData) ); + wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc), + .dat_i(wb_dat_i), .dat_o(CtrlData) ); // MIICOMMAND register - needs special treatment because of auto-resetting bits always @ (posedge wb_clk) if (wb_rst) MIICOMMAND <= 0; else - if (wr_acc & (wb_adr == 8'd8)) + if (wr_acc & (wb_adr[7:2] == 6'd8)) MIICOMMAND <= wb_dat_i; else begin @@ -129,7 +132,7 @@ module simple_gemac_wb .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) ); always @(posedge wb_clk) - case(wb_adr) + case(wb_adr[7:2]) 0 : wb_dat_o <= misc_settings; 1 : wb_dat_o <= ucast_addr[47:32]; 2 : wb_dat_o <= ucast_addr[31:0]; @@ -141,6 +144,6 @@ module simple_gemac_wb 8 : wb_dat_o <= MIICOMMAND; 9 : wb_dat_o <= MIISTATUS; 10: wb_dat_o <= MIIRX_DATA; - endcase // case (wb_adr) + endcase // case (wb_adr[7:2]) endmodule // simple_gemac_wb |