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authorJohnathan Corgan <jcorgan@corganenterprises.com>2009-10-01 11:00:25 -0700
committerJohnathan Corgan <jcorgan@corganenterprises.com>2009-10-01 11:07:59 -0700
commit1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (patch)
tree04f94ef4f7f06a210f7532592829332c7f2621f0 /opencores/wb_conbus/bench/verilog
parent7b8f65256b5ea300187ebb6a359df2fa707a295d (diff)
parent42fc55415af499980901c7787f44c7e74b4a9ce1 (diff)
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Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits) Fix warnings, mostly from implicitly defined wires or unspecified widths fullchip sim now compiles again, after moving eth and models over to new simple_gemac remove unused opencores remove debugging code no idea where this came from, it shouldn't be here Copied wb_1master back from quad radio Remove old mac. Good riddance. remove unused port More xilinx fifos, more clean up of our fifos might as well use a cascade fifo to help timing and give a little more capacity fix a typo which caused tx glitches Untested fixes for getting serdes onto the new fifo system. Compiles, at least Implement Eth flow control using pause frames parameterized fifo sizes, some reformatting remove unused old style fifo allow control of whether or not to honor flow control, adds some debug lines debug the rx side no longer used, replaced by newfifo version remove special last_line adjustment from ethernet port Firmware now inserts mac source address value in each frame. ...
Diffstat (limited to 'opencores/wb_conbus/bench/verilog')
-rw-r--r--opencores/wb_conbus/bench/verilog/CVS/Entries6
-rw-r--r--opencores/wb_conbus/bench/verilog/CVS/Repository1
-rw-r--r--opencores/wb_conbus/bench/verilog/CVS/Root1
-rw-r--r--opencores/wb_conbus/bench/verilog/CVS/Template0
-rw-r--r--opencores/wb_conbus/bench/verilog/tb_wb_conbus_top.v759
-rw-r--r--opencores/wb_conbus/bench/verilog/tests.v828
-rw-r--r--opencores/wb_conbus/bench/verilog/wb_mast_model.v693
-rw-r--r--opencores/wb_conbus/bench/verilog/wb_model_defines.v64
-rw-r--r--opencores/wb_conbus/bench/verilog/wb_slv_model.v167
9 files changed, 0 insertions, 2519 deletions
diff --git a/opencores/wb_conbus/bench/verilog/CVS/Entries b/opencores/wb_conbus/bench/verilog/CVS/Entries
deleted file mode 100644
index 76919de45..000000000
--- a/opencores/wb_conbus/bench/verilog/CVS/Entries
+++ /dev/null
@@ -1,6 +0,0 @@
-/tb_wb_conbus_top.v/1.1.1.1/Sat Apr 19 08:40:17 2003//
-/tests.v/1.1.1.1/Sat Apr 19 08:40:17 2003//
-/wb_mast_model.v/1.1.1.1/Sat Apr 19 08:40:15 2003//
-/wb_model_defines.v/1.1.1.1/Sat Apr 19 08:40:16 2003//
-/wb_slv_model.v/1.1.1.1/Sat Apr 19 08:40:16 2003//
-D
diff --git a/opencores/wb_conbus/bench/verilog/CVS/Repository b/opencores/wb_conbus/bench/verilog/CVS/Repository
deleted file mode 100644
index 306445302..000000000
--- a/opencores/wb_conbus/bench/verilog/CVS/Repository
+++ /dev/null
@@ -1 +0,0 @@
-wb_conbus/bench/verilog
diff --git a/opencores/wb_conbus/bench/verilog/CVS/Root b/opencores/wb_conbus/bench/verilog/CVS/Root
deleted file mode 100644
index 44b2aa23b..000000000
--- a/opencores/wb_conbus/bench/verilog/CVS/Root
+++ /dev/null
@@ -1 +0,0 @@
-:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/opencores/wb_conbus/bench/verilog/CVS/Template b/opencores/wb_conbus/bench/verilog/CVS/Template
deleted file mode 100644
index e69de29bb..000000000
--- a/opencores/wb_conbus/bench/verilog/CVS/Template
+++ /dev/null
diff --git a/opencores/wb_conbus/bench/verilog/tb_wb_conbus_top.v b/opencores/wb_conbus/bench/verilog/tb_wb_conbus_top.v
deleted file mode 100644
index e15d089f3..000000000
--- a/opencores/wb_conbus/bench/verilog/tb_wb_conbus_top.v
+++ /dev/null
@@ -1,759 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Top Level Test Bench ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-
-//
-//
-// rewrite from test the wb_conbus module
-//
-//
-
-
-`include "wb_conbus_defines.v"
-
-module tb_wb_conbus;
-
-reg clk;
-reg rst;
-
-// IO Prototypes
-wire [31:0] m0_data_i;
-wire [31:0] m0_data_o;
-wire [31:0] m0_addr_i;
-wire [3:0] m0_sel_i;
-wire m0_we_i;
-wire m0_cyc_i;
-wire m0_stb_i;
-wire m0_ack_o;
-wire m0_err_o;
-wire m0_rty_o;
-wire [31:0] m1_data_i;
-wire [31:0] m1_data_o;
-wire [31:0] m1_addr_i;
-wire [3:0] m1_sel_i;
-wire m1_we_i;
-wire m1_cyc_i;
-wire m1_stb_i;
-wire m1_ack_o;
-wire m1_err_o;
-wire m1_rty_o;
-wire [31:0] m2_data_i;
-wire [31:0] m2_data_o;
-wire [31:0] m2_addr_i;
-wire [3:0] m2_sel_i;
-wire m2_we_i;
-wire m2_cyc_i;
-wire m2_stb_i;
-wire m2_ack_o;
-wire m2_err_o;
-wire m2_rty_o;
-wire [31:0] m3_data_i;
-wire [31:0] m3_data_o;
-wire [31:0] m3_addr_i;
-wire [3:0] m3_sel_i;
-wire m3_we_i;
-wire m3_cyc_i;
-wire m3_stb_i;
-wire m3_ack_o;
-wire m3_err_o;
-wire m3_rty_o;
-wire [31:0] m4_data_i;
-wire [31:0] m4_data_o;
-wire [31:0] m4_addr_i;
-wire [3:0] m4_sel_i;
-wire m4_we_i;
-wire m4_cyc_i;
-wire m4_stb_i;
-wire m4_ack_o;
-wire m4_err_o;
-wire m4_rty_o;
-wire [31:0] m5_data_i;
-wire [31:0] m5_data_o;
-wire [31:0] m5_addr_i;
-wire [3:0] m5_sel_i;
-wire m5_we_i;
-wire m5_cyc_i;
-wire m5_stb_i;
-wire m5_ack_o;
-wire m5_err_o;
-wire m5_rty_o;
-wire [31:0] m6_data_i;
-wire [31:0] m6_data_o;
-wire [31:0] m6_addr_i;
-wire [3:0] m6_sel_i;
-wire m6_we_i;
-wire m6_cyc_i;
-wire m6_stb_i;
-wire m6_ack_o;
-wire m6_err_o;
-wire m6_rty_o;
-wire [31:0] m7_data_i;
-wire [31:0] m7_data_o;
-wire [31:0] m7_addr_i;
-wire [3:0] m7_sel_i;
-wire m7_we_i;
-wire m7_cyc_i;
-wire m7_stb_i;
-wire m7_ack_o;
-wire m7_err_o;
-wire m7_rty_o;
-wire [31:0] s0_data_i;
-wire [31:0] s0_data_o;
-wire [31:0] s0_addr_o;
-wire [3:0] s0_sel_o;
-wire s0_we_o;
-wire s0_cyc_o;
-wire s0_stb_o;
-wire s0_ack_i;
-wire s0_err_i;
-wire s0_rty_i;
-wire [31:0] s1_data_i;
-wire [31:0] s1_data_o;
-wire [31:0] s1_addr_o;
-wire [3:0] s1_sel_o;
-wire s1_we_o;
-wire s1_cyc_o;
-wire s1_stb_o;
-wire s1_ack_i;
-wire s1_err_i;
-wire s1_rty_i;
-wire [31:0] s2_data_i;
-wire [31:0] s2_data_o;
-wire [31:0] s2_addr_o;
-wire [3:0] s2_sel_o;
-wire s2_we_o;
-wire s2_cyc_o;
-wire s2_stb_o;
-wire s2_ack_i;
-wire s2_err_i;
-wire s2_rty_i;
-wire [31:0] s3_data_i;
-wire [31:0] s3_data_o;
-wire [31:0] s3_addr_o;
-wire [3:0] s3_sel_o;
-wire s3_we_o;
-wire s3_cyc_o;
-wire s3_stb_o;
-wire s3_ack_i;
-wire s3_err_i;
-wire s3_rty_i;
-wire [31:0] s4_data_i;
-wire [31:0] s4_data_o;
-wire [31:0] s4_addr_o;
-wire [3:0] s4_sel_o;
-wire s4_we_o;
-wire s4_cyc_o;
-wire s4_stb_o;
-wire s4_ack_i;
-wire s4_err_i;
-wire s4_rty_i;
-wire [31:0] s5_data_i;
-wire [31:0] s5_data_o;
-wire [31:0] s5_addr_o;
-wire [3:0] s5_sel_o;
-wire s5_we_o;
-wire s5_cyc_o;
-wire s5_stb_o;
-wire s5_ack_i;
-wire s5_err_i;
-wire s5_rty_i;
-wire [31:0] s6_data_i;
-wire [31:0] s6_data_o;
-wire [31:0] s6_addr_o;
-wire [3:0] s6_sel_o;
-wire s6_we_o;
-wire s6_cyc_o;
-wire s6_stb_o;
-wire s6_ack_i;
-wire s6_err_i;
-wire s6_rty_i;
-wire [31:0] s7_data_i;
-wire [31:0] s7_data_o;
-wire [31:0] s7_addr_o;
-wire [3:0] s7_sel_o;
-wire s7_we_o;
-wire s7_cyc_o;
-wire s7_stb_o;
-wire s7_ack_i;
-wire s7_err_i;
-wire s7_rty_i;
-
-
-
-// Test Bench Variables
-reg [31:0] wd_cnt;
-integer error_cnt;
-integer verbose;
-
-// Misc Variables
-
-/////////////////////////////////////////////////////////////////////
-//
-// Defines
-//
-
-
-/////////////////////////////////////////////////////////////////////
-//
-// Simulation Initialization and Start up Section
-//
-
-
-initial
- begin
- $timeformat (-9, 1, " ns", 10);
-
- $display("\n\n");
- $display("*****************************************************");
- $display("* WISHBONE Connection Matrix Simulation started ... *");
- $display("*****************************************************");
- $display("\n");
-
-`ifdef WAVES
- $shm_open("waves");
- $shm_probe("AS",test,"AS");
- $display("INFO: Signal dump enabled ...\n\n");
-`endif
- wd_cnt = 0;
- error_cnt = 0;
- clk = 1;
- rst = 1;
- verbose = 1;
-
- repeat(5) @(posedge clk);
- s0.delay = 1;
- s1.delay = 1;
- s2.delay = 1;
- s3.delay = 1;
- s4.delay = 1;
- s5.delay = 1;
- s6.delay = 1;
- s7.delay = 1;
-
- #1;
- rst = 0;
- repeat(5) @(posedge clk);
-
- // HERE IS WHERE THE TEST CASES GO ...
-
-if(1) // Full Regression Run
- begin
- $display(" ......................................................");
- $display(" : :");
- $display(" : Regression Run ... :");
- $display(" :....................................................:");
- verbose = 0;
-
- test_dp1;
-// test_rf;
-// test_arb1;
-// test_arb2;
- test_dp2;
-
- end
-else
-if(1) // Debug Tests
- begin
- $display(" ......................................................");
- $display(" : :");
- $display(" : Test Debug Testing ... :");
- $display(" :....................................................:");
-
- test_dp2;
-
- end
-
-repeat(100) @(posedge clk);
-$finish;
-end // End of Initial
-
-/////////////////////////////////////////////////////////////////////
-//
-// Clock Generation
-//
-
-always #5 clk = ~clk;
-
-/////////////////////////////////////////////////////////////////////
-//
-// Watchdog Counter
-//
-
-always @(posedge clk)
- if(m0_ack_o | m1_ack_o | m2_ack_o | m3_ack_o |
- m4_ack_o | m5_ack_o | m6_ack_o | m7_ack_o)
- wd_cnt = 0;
- else
- wd_cnt = wd_cnt +1;
-
-always @(wd_cnt)
- if(wd_cnt > 5000000)
- begin
- $display("\n*******************************************");
- $display("*** ERROR: Watchdog Counter Expired ... ***");
- $display("*******************************************\n");
- $finish;
- end
-
-/////////////////////////////////////////////////////////////////////
-//
-// IO Monitors
-//
-
-/////////////////////////////////////////////////////////////////////
-//
-// WISHBONE Inter Connect
-//
-
-wb_conbus_top #(4,
- 4'h0,
- 4,
- 4'h1,
- 4,
- 4'h2,
- 4'h3,
- 4'h4,
- 4'h5,
- 4'h6,
- 4'h7
- )
- conbus(
- .clk_i( clk ),
- .rst_i( rst ),
- .m0_dat_i( m0_data_i ),
- .m0_dat_o( m0_data_o ),
- .m0_adr_i( m0_addr_i ),
- .m0_sel_i( m0_sel_i ),
- .m0_we_i( m0_we_i ),
- .m0_cyc_i( m0_cyc_i ),
- .m0_stb_i( m0_stb_i ),
- .m0_ack_o( m0_ack_o ),
- .m0_err_o( m0_err_o ),
- .m0_rty_o( m0_rty_o ),
- .m1_dat_i( m1_data_i ),
- .m1_dat_o( m1_data_o ),
- .m1_adr_i( m1_addr_i ),
- .m1_sel_i( m1_sel_i ),
- .m1_we_i( m1_we_i ),
- .m1_cyc_i( m1_cyc_i ),
- .m1_stb_i( m1_stb_i ),
- .m1_ack_o( m1_ack_o ),
- .m1_err_o( m1_err_o ),
- .m1_rty_o( m1_rty_o ),
- .m2_dat_i( m2_data_i ),
- .m2_dat_o( m2_data_o ),
- .m2_adr_i( m2_addr_i ),
- .m2_sel_i( m2_sel_i ),
- .m2_we_i( m2_we_i ),
- .m2_cyc_i( m2_cyc_i ),
- .m2_stb_i( m2_stb_i ),
- .m2_ack_o( m2_ack_o ),
- .m2_err_o( m2_err_o ),
- .m2_rty_o( m2_rty_o ),
- .m3_dat_i( m3_data_i ),
- .m3_dat_o( m3_data_o ),
- .m3_adr_i( m3_addr_i ),
- .m3_sel_i( m3_sel_i ),
- .m3_we_i( m3_we_i ),
- .m3_cyc_i( m3_cyc_i ),
- .m3_stb_i( m3_stb_i ),
- .m3_ack_o( m3_ack_o ),
- .m3_err_o( m3_err_o ),
- .m3_rty_o( m3_rty_o ),
- .m4_dat_i( m4_data_i ),
- .m4_dat_o( m4_data_o ),
- .m4_adr_i( m4_addr_i ),
- .m4_sel_i( m4_sel_i ),
- .m4_we_i( m4_we_i ),
- .m4_cyc_i( m4_cyc_i ),
- .m4_stb_i( m4_stb_i ),
- .m4_ack_o( m4_ack_o ),
- .m4_err_o( m4_err_o ),
- .m4_rty_o( m4_rty_o ),
- .m5_dat_i( m5_data_i ),
- .m5_dat_o( m5_data_o ),
- .m5_adr_i( m5_addr_i ),
- .m5_sel_i( m5_sel_i ),
- .m5_we_i( m5_we_i ),
- .m5_cyc_i( m5_cyc_i ),
- .m5_stb_i( m5_stb_i ),
- .m5_ack_o( m5_ack_o ),
- .m5_err_o( m5_err_o ),
- .m5_rty_o( m5_rty_o ),
- .m6_dat_i( m6_data_i ),
- .m6_dat_o( m6_data_o ),
- .m6_adr_i( m6_addr_i ),
- .m6_sel_i( m6_sel_i ),
- .m6_we_i( m6_we_i ),
- .m6_cyc_i( m6_cyc_i ),
- .m6_stb_i( m6_stb_i ),
- .m6_ack_o( m6_ack_o ),
- .m6_err_o( m6_err_o ),
- .m6_rty_o( m6_rty_o ),
- .m7_dat_i( m7_data_i ),
- .m7_dat_o( m7_data_o ),
- .m7_adr_i( m7_addr_i ),
- .m7_sel_i( m7_sel_i ),
- .m7_we_i( m7_we_i ),
- .m7_cyc_i( m7_cyc_i ),
- .m7_stb_i( m7_stb_i ),
- .m7_ack_o( m7_ack_o ),
- .m7_err_o( m7_err_o ),
- .m7_rty_o( m7_rty_o ),
- .s0_dat_i( s0_data_i ),
- .s0_dat_o( s0_data_o ),
- .s0_adr_o( s0_addr_o ),
- .s0_sel_o( s0_sel_o ),
- .s0_we_o( s0_we_o ),
- .s0_cyc_o( s0_cyc_o ),
- .s0_stb_o( s0_stb_o ),
- .s0_ack_i( s0_ack_i ),
- .s0_err_i( s0_err_i ),
- .s0_rty_i( s0_rty_i ),
- .s1_dat_i( s1_data_i ),
- .s1_dat_o( s1_data_o ),
- .s1_adr_o( s1_addr_o ),
- .s1_sel_o( s1_sel_o ),
- .s1_we_o( s1_we_o ),
- .s1_cyc_o( s1_cyc_o ),
- .s1_stb_o( s1_stb_o ),
- .s1_ack_i( s1_ack_i ),
- .s1_err_i( s1_err_i ),
- .s1_rty_i( s1_rty_i ),
- .s2_dat_i( s2_data_i ),
- .s2_dat_o( s2_data_o ),
- .s2_adr_o( s2_addr_o ),
- .s2_sel_o( s2_sel_o ),
- .s2_we_o( s2_we_o ),
- .s2_cyc_o( s2_cyc_o ),
- .s2_stb_o( s2_stb_o ),
- .s2_ack_i( s2_ack_i ),
- .s2_err_i( s2_err_i ),
- .s2_rty_i( s2_rty_i ),
- .s3_dat_i( s3_data_i ),
- .s3_dat_o( s3_data_o ),
- .s3_adr_o( s3_addr_o ),
- .s3_sel_o( s3_sel_o ),
- .s3_we_o( s3_we_o ),
- .s3_cyc_o( s3_cyc_o ),
- .s3_stb_o( s3_stb_o ),
- .s3_ack_i( s3_ack_i ),
- .s3_err_i( s3_err_i ),
- .s3_rty_i( s3_rty_i ),
- .s4_dat_i( s4_data_i ),
- .s4_dat_o( s4_data_o ),
- .s4_adr_o( s4_addr_o ),
- .s4_sel_o( s4_sel_o ),
- .s4_we_o( s4_we_o ),
- .s4_cyc_o( s4_cyc_o ),
- .s4_stb_o( s4_stb_o ),
- .s4_ack_i( s4_ack_i ),
- .s4_err_i( s4_err_i ),
- .s4_rty_i( s4_rty_i ),
- .s5_dat_i( s5_data_i ),
- .s5_dat_o( s5_data_o ),
- .s5_adr_o( s5_addr_o ),
- .s5_sel_o( s5_sel_o ),
- .s5_we_o( s5_we_o ),
- .s5_cyc_o( s5_cyc_o ),
- .s5_stb_o( s5_stb_o ),
- .s5_ack_i( s5_ack_i ),
- .s5_err_i( s5_err_i ),
- .s5_rty_i( s5_rty_i ),
- .s6_dat_i( s6_data_i ),
- .s6_dat_o( s6_data_o ),
- .s6_adr_o( s6_addr_o ),
- .s6_sel_o( s6_sel_o ),
- .s6_we_o( s6_we_o ),
- .s6_cyc_o( s6_cyc_o ),
- .s6_stb_o( s6_stb_o ),
- .s6_ack_i( s6_ack_i ),
- .s6_err_i( s6_err_i ),
- .s6_rty_i( s6_rty_i ),
- .s7_dat_i( s7_data_i ),
- .s7_dat_o( s7_data_o ),
- .s7_adr_o( s7_addr_o ),
- .s7_sel_o( s7_sel_o ),
- .s7_we_o( s7_we_o ),
- .s7_cyc_o( s7_cyc_o ),
- .s7_stb_o( s7_stb_o ),
- .s7_ack_i( s7_ack_i ),
- .s7_err_i( s7_err_i ),
- .s7_rty_i( s7_rty_i )
- );
-
-
-/////////////////////////////////////////////////////////////////////
-//
-// WISHBONE Master Models
-//
-
-wb_mast m0( .clk( clk ),
- .rst( ~rst ),
- .adr( m0_addr_i ),
- .din( m0_data_o ),
- .dout( m0_data_i ),
- .cyc( m0_cyc_i ),
- .stb( m0_stb_i ),
- .sel( m0_sel_i ),
- .we( m0_we_i ),
- .ack( m0_ack_o ),
- .err( m0_err_o ),
- .rty( m0_rty_o )
- );
-
-wb_mast m1( .clk( clk ),
- .rst( ~rst ),
- .adr( m1_addr_i ),
- .din( m1_data_o ),
- .dout( m1_data_i ),
- .cyc( m1_cyc_i ),
- .stb( m1_stb_i ),
- .sel( m1_sel_i ),
- .we( m1_we_i ),
- .ack( m1_ack_o ),
- .err( m1_err_o ),
- .rty( m1_rty_o )
- );
-
-wb_mast m2( .clk( clk ),
- .rst( ~rst ),
- .adr( m2_addr_i ),
- .din( m2_data_o ),
- .dout( m2_data_i ),
- .cyc( m2_cyc_i ),
- .stb( m2_stb_i ),
- .sel( m2_sel_i ),
- .we( m2_we_i ),
- .ack( m2_ack_o ),
- .err( m2_err_o ),
- .rty( m2_rty_o )
- );
-
-wb_mast m3( .clk( clk ),
- .rst( ~rst ),
- .adr( m3_addr_i ),
- .din( m3_data_o ),
- .dout( m3_data_i ),
- .cyc( m3_cyc_i ),
- .stb( m3_stb_i ),
- .sel( m3_sel_i ),
- .we( m3_we_i ),
- .ack( m3_ack_o ),
- .err( m3_err_o ),
- .rty( m3_rty_o )
- );
-
-wb_mast m4( .clk( clk ),
- .rst( ~rst ),
- .adr( m4_addr_i ),
- .din( m4_data_o ),
- .dout( m4_data_i ),
- .cyc( m4_cyc_i ),
- .stb( m4_stb_i ),
- .sel( m4_sel_i ),
- .we( m4_we_i ),
- .ack( m4_ack_o ),
- .err( m4_err_o ),
- .rty( m4_rty_o )
- );
-
-wb_mast m5( .clk( clk ),
- .rst( ~rst ),
- .adr( m5_addr_i ),
- .din( m5_data_o ),
- .dout( m5_data_i ),
- .cyc( m5_cyc_i ),
- .stb( m5_stb_i ),
- .sel( m5_sel_i ),
- .we( m5_we_i ),
- .ack( m5_ack_o ),
- .err( m5_err_o ),
- .rty( m5_rty_o )
- );
-
-wb_mast m6( .clk( clk ),
- .rst( ~rst ),
- .adr( m6_addr_i ),
- .din( m6_data_o ),
- .dout( m6_data_i ),
- .cyc( m6_cyc_i ),
- .stb( m6_stb_i ),
- .sel( m6_sel_i ),
- .we( m6_we_i ),
- .ack( m6_ack_o ),
- .err( m6_err_o ),
- .rty( m6_rty_o )
- );
-
-wb_mast m7( .clk( clk ),
- .rst( ~rst ),
- .adr( m7_addr_i ),
- .din( m7_data_o ),
- .dout( m7_data_i ),
- .cyc( m7_cyc_i ),
- .stb( m7_stb_i ),
- .sel( m7_sel_i ),
- .we( m7_we_i ),
- .ack( m7_ack_o ),
- .err( m7_err_o ),
- .rty( m7_rty_o )
- );
-
-
-/////////////////////////////////////////////////////////////////////
-//
-// WISHBONE Slave Models
-//
-
-wb_slv s0( .clk( clk ),
- .rst( ~rst ),
- .adr( s0_addr_o ),
- .din( s0_data_o ),
- .dout( s0_data_i ),
- .cyc( s0_cyc_o ),
- .stb( s0_stb_o ),
- .sel( s0_sel_o ),
- .we( s0_we_o ),
- .ack( s0_ack_i ),
- .err( s0_err_i ),
- .rty( s0_rty_i )
- );
-
-wb_slv s1( .clk( clk ),
- .rst( ~rst ),
- .adr( s1_addr_o ),
- .din( s1_data_o ),
- .dout( s1_data_i ),
- .cyc( s1_cyc_o ),
- .stb( s1_stb_o ),
- .sel( s1_sel_o ),
- .we( s1_we_o ),
- .ack( s1_ack_i ),
- .err( s1_err_i ),
- .rty( s1_rty_i )
- );
-
-wb_slv s2( .clk( clk ),
- .rst( ~rst ),
- .adr( s2_addr_o ),
- .din( s2_data_o ),
- .dout( s2_data_i ),
- .cyc( s2_cyc_o ),
- .stb( s2_stb_o ),
- .sel( s2_sel_o ),
- .we( s2_we_o ),
- .ack( s2_ack_i ),
- .err( s2_err_i ),
- .rty( s2_rty_i )
- );
-
-wb_slv s3( .clk( clk ),
- .rst( ~rst ),
- .adr( s3_addr_o ),
- .din( s3_data_o ),
- .dout( s3_data_i ),
- .cyc( s3_cyc_o ),
- .stb( s3_stb_o ),
- .sel( s3_sel_o ),
- .we( s3_we_o ),
- .ack( s3_ack_i ),
- .err( s3_err_i ),
- .rty( s3_rty_i )
- );
-
-wb_slv s4( .clk( clk ),
- .rst( ~rst ),
- .adr( s4_addr_o ),
- .din( s4_data_o ),
- .dout( s4_data_i ),
- .cyc( s4_cyc_o ),
- .stb( s4_stb_o ),
- .sel( s4_sel_o ),
- .we( s4_we_o ),
- .ack( s4_ack_i ),
- .err( s4_err_i ),
- .rty( s4_rty_i )
- );
-
-wb_slv s5( .clk( clk ),
- .rst( ~rst ),
- .adr( s5_addr_o ),
- .din( s5_data_o ),
- .dout( s5_data_i ),
- .cyc( s5_cyc_o ),
- .stb( s5_stb_o ),
- .sel( s5_sel_o ),
- .we( s5_we_o ),
- .ack( s5_ack_i ),
- .err( s5_err_i ),
- .rty( s5_rty_i )
- );
-
-wb_slv s6( .clk( clk ),
- .rst( ~rst ),
- .adr( s6_addr_o ),
- .din( s6_data_o ),
- .dout( s6_data_i ),
- .cyc( s6_cyc_o ),
- .stb( s6_stb_o ),
- .sel( s6_sel_o ),
- .we( s6_we_o ),
- .ack( s6_ack_i ),
- .err( s6_err_i ),
- .rty( s6_rty_i )
- );
-
-wb_slv s7( .clk( clk ),
- .rst( ~rst ),
- .adr( s7_addr_o ),
- .din( s7_data_o ),
- .dout( s7_data_i ),
- .cyc( s7_cyc_o ),
- .stb( s7_stb_o ),
- .sel( s7_sel_o ),
- .we( s7_we_o ),
- .ack( s7_ack_i ),
- .err( s7_err_i ),
- .rty( s7_rty_i )
- );
-
-
-`include "tests.v"
-
-endmodule
-
diff --git a/opencores/wb_conbus/bench/verilog/tests.v b/opencores/wb_conbus/bench/verilog/tests.v
deleted file mode 100644
index 5067f2696..000000000
--- a/opencores/wb_conbus/bench/verilog/tests.v
+++ /dev/null
@@ -1,828 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// WISHBONE Connection Matrix Test Cases ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000 Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: tests.v,v 1.1.1.1 2003/04/19 08:40:17 johny Exp $
-//
-// $Date: 2003/04/19 08:40:17 $
-// $Revision: 1.1.1.1 $
-// $Author: johny $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: tests.v,v $
-// Revision 1.1.1.1 2003/04/19 08:40:17 johny
-// no message
-//
-// Revision 1.1.1.1 2001/10/19 11:04:27 rudi
-// WISHBONE CONMAX IP Core
-//
-//
-//
-//
-//
-//
-
-
-task show_errors;
-
-begin
-
-$display("\n");
-$display(" +--------------------+");
-$display(" | Total ERRORS: %0d |", error_cnt);
-$display(" +--------------------+");
-
-end
-endtask
-
-
-task init_all_mem;
-
-begin
- s0.fill_mem(1);
- s1.fill_mem(1);
- s2.fill_mem(1);
- s3.fill_mem(1);
- s4.fill_mem(1);
- s5.fill_mem(1);
- s6.fill_mem(1);
- s7.fill_mem(1);
-
-
- m0.mem_fill;
- m1.mem_fill;
- m2.mem_fill;
- m3.mem_fill;
- m4.mem_fill;
- m5.mem_fill;
- m6.mem_fill;
- m7.mem_fill;
-
-end
-endtask
-
-
-task verify;
-input master;
-input slave;
-input count;
-
-integer master, slave, count;
-begin
-verify_sub(master,slave,count,0,0);
-end
-endtask
-
-
-task verify_sub;
-input master;
-input slave;
-input count;
-input mo;
-input so;
-
-integer master, slave, count;
-integer mo, so;
-integer o;
-integer n;
-reg [31:0] mdata, sdata;
-
-begin
-
-//$display("V2: %0d %0d %0d %0d %0d",master, slave, count, mo,so);
-
-for(n=0;n<count;n=n+1)
- begin
- case(master)
- 0: mdata = m0.mem[n+mo];
- 1: mdata = m1.mem[n+mo];
- 2: mdata = m2.mem[n+mo];
- 3: mdata = m3.mem[n+mo];
- 4: mdata = m4.mem[n+mo];
- 5: mdata = m5.mem[n+mo];
- 6: mdata = m6.mem[n+mo];
- 7: mdata = m7.mem[n+mo];
- default:
- begin
- $display("ERROR: Illegal Master %0d", master);
- $finish;
- end
- endcase
-
- o = 0;
- case(master)
- 0: o = 16'h000;
- 1: o = 16'h040;
- 2: o = 16'h080;
- 3: o = 16'h0c0;
- 4: o = 16'h100;
- 5: o = 16'h140;
- 6: o = 16'h180;
- 7: o = 16'h1c0;
- endcase
-
- case(slave)
- 0: sdata = s0.mem[n+o+so];
- 1: sdata = s1.mem[n+o+so];
- 2: sdata = s2.mem[n+o+so];
- 3: sdata = s3.mem[n+o+so];
- 4: sdata = s4.mem[n+o+so];
- 5: sdata = s5.mem[n+o+so];
- 6: sdata = s6.mem[n+o+so];
- 7: sdata = s7.mem[n+o+so];
- default:
- begin
- $display("ERROR: Illegal Slave %0d", slave);
- $finish;
- end
- endcase
-
- //$display("INFO: Master[%0d]: %h - Slave[%0d]: %h (%0t)",
- // master, mdata, slave, sdata, $time);
-
- if(mdata !== sdata)
- begin
- $display("ERROR: Master[%0d][%0d]: %h - Slave[%0d]: %h (%0t)",
- master, n, mdata, slave, sdata, $time);
- error_cnt = error_cnt + 1;
- end
- end
-end
-
-endtask
-
-
-task test_arb1;
-
-integer n, del;
-reg [31:0] data;
-
-begin
-
- $display("\n\n");
- $display("*****************************************************");
- $display("*** Arb. 1 Test ... ***");
- $display("*****************************************************\n");
-
-del = 4;
-for(del = 0;del < 5; del=del+1 )
- begin
- $display("Delay: %0d", del);
- init_all_mem;
- m1.wb_wr1( 32'hff00_0000, 4'hf, 32'h0000_a5ff);
-
- fork
- begin
- m0.wb_rd_mult( 32'h0000_0000 + (0 << 28), 4'hf, del, 4);
- m0.wb_rd1( 32'hff00_0000, 4'hf, data);
- if(data !== 32'h0000_a5ff)
- begin
- $display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
- error_cnt = error_cnt + 1;
- end
- m0.wb_wr_mult( 32'h0000_0010 + (0 << 28), 4'hf, del, 4);
- m0.wb_rd_mult( 32'h0000_0020 + (0 << 28), 4'hf, del, 4);
- m0.wb_wr_mult( 32'h0000_0030 + (0 << 28), 4'hf, del, 4);
- end
-
- begin
- m1.wb_wr_mult( 32'h0000_0100 + (0 << 28), 4'hf, del, 4);
- m1.wb_rd_mult( 32'h0000_0110 + (0 << 28), 4'hf, del, 4);
- m1.wb_rd1( 32'hff00_0000, 4'hf, data);
- if(data !== 32'h0000_a5ff)
- begin
- $display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
- error_cnt = error_cnt + 1;
- end
- m1.wb_wr_mult( 32'h0000_0120 + (0 << 28), 4'hf, del, 4);
- m1.wb_rd_mult( 32'h0000_0130 + (0 << 28), 4'hf, del, 4);
- end
-
- begin
- m2.wb_rd_mult( 32'h0000_0200 + (0 << 28), 4'hf, del, 4);
- m2.wb_wr_mult( 32'h0000_0210 + (0 << 28), 4'hf, del, 4);
- m2.wb_rd_mult( 32'h0000_0220 + (0 << 28), 4'hf, del, 4);
- m2.wb_rd1( 32'hff00_0000, 4'hf, data);
- if(data !== 32'h0000_a5ff)
- begin
- $display("ERROR: RF read mismatch: Exp. 0, Got %h", data);
- error_cnt = error_cnt + 1;
- end
- m2.wb_wr_mult( 32'h0000_0230 + (0 << 28), 4'hf, del, 4);
- end
-
- begin
- m3.wb_wr_mult( 32'h0000_0300 + (0 << 28), 4'hf, del, 4);
- m3.wb_rd_mult( 32'h0000_0310 + (0 << 28), 4'hf, del, 4);
- m3.wb_wr_mult( 32'h0000_0320 + (0 << 28), 4'hf, del, 4);
- m3.wb_rd_mult( 32'h0000_0330 + (0 << 28), 4'hf, del, 4);
- m3.wb_rd1( 32'hff00_0000, 4'hf, data);
- if(data !== 32'h0000_a5ff)
- begin
- $display("ERROR: RF read mismatch: Exp. a5ff, Got %h", data);
- error_cnt = error_cnt + 1;
- end
- end
-
- begin
- m4.wb_rd_mult( 32'h0000_0400 + (1 << 28), 4'hf, del, 4);
- m4.wb_wr_mult( 32'h0000_0410 + (1 << 28), 4'hf, del, 4);
- m4.wb_rd_mult( 32'h0000_0420 + (1 << 28), 4'hf, del, 4);
- m4.wb_wr_mult( 32'h0000_0430 + (1 << 28), 4'hf, del, 4);
- end
-
- begin
- m5.wb_rd_mult( 32'h0000_0500 + (1 << 28), 4'hf, del, 4);
- m5.wb_wr_mult( 32'h0000_0510 + (1 << 28), 4'hf, del, 4);
- m5.wb_rd_mult( 32'h0000_0520 + (1 << 28), 4'hf, del, 4);
- m5.wb_wr_mult( 32'h0000_0530 + (1 << 28), 4'hf, del, 4);
- end
-
- begin
- m6.wb_wr_mult( 32'h0000_0600 + (7 << 28), 4'hf, del, 4);
- m6.wb_rd_mult( 32'h0000_0610 + (7 << 28), 4'hf, del, 4);
- m6.wb_wr_mult( 32'h0000_0620 + (7 << 28), 4'hf, del, 4);
- m6.wb_rd_mult( 32'h0000_0630 + (7 << 28), 4'hf, del, 4);
- end
-
- begin
- m7.wb_wr_mult( 32'h0000_0700 + (7 << 28), 4'hf, del, 4);
- m7.wb_rd_mult( 32'h0000_0710 + (7 << 28), 4'hf, del, 4);
- m7.wb_wr_mult( 32'h0000_0720 + (7 << 28), 4'hf, del, 4);
- m7.wb_rd_mult( 32'h0000_0730 + (7 << 28), 4'hf, del, 4);
- end
- join
-
- verify(0,0,16);
- verify(1,0,16);
- verify(2,0,16);
- verify(3,0,16);
- verify(4,1,16);
- verify(5,1,16);
- verify(6,7,16);
- verify(7,7,16);
- end
- show_errors;
- $display("*****************************************************");
- $display("*** Test DONE ... ***");
- $display("*****************************************************\n\n");
-
-end
-endtask
-
-
-task test_arb2;
-
-integer m, del, siz;
-integer n, a, b;
-time t[0:7];
-reg [1:0] p[0:7];
-
-begin
-
- $display("\n\n");
- $display("*****************************************************");
- $display("*** Arb. 2 Test ... ***");
- $display("*****************************************************\n");
-
-
-siz = 4;
-del = 0;
-m=0;
-for(m=0;m<32;m=m+1)
-for(del=0;del<7;del=del+1)
-for(siz=1;siz<5;siz=siz+1)
- begin
-
- init_all_mem;
- $display("Mode: %0d del: %0d, siz: %0d", m, del, siz);
-
- case(m)
- 0:
- begin
- p[7] = 2'd3; // M 7
- p[6] = 2'd1; // M 6
- p[5] = 2'd2; // M 5
- p[4] = 2'd3; // M 4
- p[3] = 2'd0; // M 3
- p[2] = 2'd1; // M 2
- p[1] = 2'd0; // M 1
- p[0] = 2'd2; // M 0
- end
-
- 4:
- begin
- p[7] = 2'd0; // M 7
- p[6] = 2'd1; // M 6
- p[5] = 2'd2; // M 5
- p[4] = 2'd3; // M 4
- p[3] = 2'd3; // M 3
- p[2] = 2'd2; // M 2
- p[1] = 2'd1; // M 1
- p[0] = 2'd0; // M 0
- end
-
- 8:
- begin
- p[7] = 2'd3; // M 7
- p[6] = 2'd2; // M 6
- p[5] = 2'd1; // M 5
- p[4] = 2'd0; // M 4
- p[3] = 2'd0; // M 3
- p[2] = 2'd1; // M 2
- p[1] = 2'd2; // M 1
- p[0] = 2'd3; // M 0
- end
-
- 12:
- begin
- p[7] = 2'd3; // M 7
- p[6] = 2'd3; // M 6
- p[5] = 2'd3; // M 5
- p[4] = 2'd0; // M 4
- p[3] = 2'd0; // M 3
- p[2] = 2'd0; // M 2
- p[1] = 2'd1; // M 1
- p[0] = 2'd1; // M 0
- end
-
- 16:
- begin
- p[7] = 2'd0; // M 7
- p[6] = 2'd0; // M 6
- p[5] = 2'd0; // M 5
- p[4] = 2'd0; // M 4
- p[3] = 2'd1; // M 3
- p[2] = 2'd1; // M 2
- p[1] = 2'd3; // M 1
- p[0] = 2'd3; // M 0
- end
-
- 20:
- begin
- p[7] = 2'd3; // M 7
- p[6] = 2'd0; // M 6
- p[5] = 2'd2; // M 5
- p[4] = 2'd0; // M 4
- p[3] = 2'd1; // M 3
- p[2] = 2'd0; // M 2
- p[1] = 2'd0; // M 1
- p[0] = 2'd0; // M 0
- end
-
- 24:
- begin
- p[7] = 2'd0; // M 7
- p[6] = 2'd0; // M 6
- p[5] = 2'd1; // M 5
- p[4] = 2'd0; // M 4
- p[3] = 2'd0; // M 3
- p[2] = 2'd2; // M 2
- p[1] = 2'd0; // M 1
- p[0] = 2'd3; // M 0
- end
-
- 28:
- begin
- p[7] = 2'd0; // M 7
- p[6] = 2'd0; // M 6
- p[5] = 2'd1; // M 5
- p[4] = 2'd0; // M 4
- p[3] = 2'd0; // M 3
- p[2] = 2'd0; // M 2
- p[1] = 2'd0; // M 1
- p[0] = 2'd3; // M 0
- end
-
- default:
- begin
- p[7] = p[7] + 1;// M 7
- p[6] = p[6] + 1;// M 6
- p[5] = p[5] + 1;// M 5
- p[4] = p[4] + 1;// M 4
- p[3] = p[3] + 1;// M 3
- p[2] = p[2] + 1;// M 2
- p[1] = p[1] + 1;// M 1
- p[0] = p[0] + 1;// M 0
- end
- endcase
-
- m1.wb_wr1( 32'hff00_0000, 4'hf, {16'h0000, p[7], p[6], p[5],
- p[4], p[3], p[2], p[1], p[0]} );
-
- @(posedge clk);
- fork
- begin
- repeat(del) @(posedge clk);
- m0.wb_wr_mult( 32'h0000_0000 , 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m0.wb_rd_mult( 32'h0000_0000 + (siz * 4), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m0.wb_wr_mult( 32'h0000_0000 + (siz * 8), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m0.wb_rd_mult( 32'h0000_0000 + (siz * 12), 4'hf, del, siz);
- t[0] = $time;
- end
-
- begin
- repeat(del) @(posedge clk);
- m1.wb_rd_mult( 32'h0000_0100 , 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m1.wb_wr_mult( 32'h0000_0100 + (siz * 4), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m1.wb_rd_mult( 32'h0000_0100 + (siz * 8), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m1.wb_wr_mult( 32'h0000_0100 + (siz * 12), 4'hf, del, siz);
- t[1] = $time;
- end
-
- begin
- repeat(del) @(posedge clk);
- m2.wb_wr_mult( 32'h0000_0200 , 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m2.wb_rd_mult( 32'h0000_0200 + (siz * 4), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m2.wb_wr_mult( 32'h0000_0200 + (siz * 8), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m2.wb_rd_mult( 32'h0000_0200 + (siz * 12), 4'hf, del, siz);
- t[2] = $time;
- end
-
- begin
- repeat(del) @(posedge clk);
- m3.wb_rd_mult( 32'h0000_0300 , 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m3.wb_wr_mult( 32'h0000_0300 + (siz * 4), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m3.wb_rd_mult( 32'h0000_0300 + (siz * 8), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m3.wb_wr_mult( 32'h0000_0300 + (siz * 12), 4'hf, del, siz);
- t[3] = $time;
- end
-
- begin
- repeat(del) @(posedge clk);
- m4.wb_wr_mult( 32'h0000_0400 , 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m4.wb_rd_mult( 32'h0000_0400 + (siz * 4), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m4.wb_wr_mult( 32'h0000_0400 + (siz * 8), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m4.wb_rd_mult( 32'h0000_0400 + (siz * 12), 4'hf, del, siz);
- t[4] = $time;
- end
-
- begin
- repeat(del) @(posedge clk);
- m5.wb_rd_mult( 32'h0000_0500 , 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m5.wb_wr_mult( 32'h0000_0500 + (siz * 4), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m5.wb_rd_mult( 32'h0000_0500 + (siz * 8), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m5.wb_wr_mult( 32'h0000_0500 + (siz * 12), 4'hf, del, siz);
- t[5] = $time;
- end
-
- begin
- repeat(del) @(posedge clk);
- m6.wb_wr_mult( 32'h0000_0600 , 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m6.wb_rd_mult( 32'h0000_0600 + (siz * 4), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m6.wb_wr_mult( 32'h0000_0600 + (siz * 8), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m6.wb_rd_mult( 32'h0000_0600 + (siz * 12), 4'hf, del, siz);
- t[6] = $time;
- end
-
- begin
- repeat(del) @(posedge clk);
- m7.wb_wr_mult( 32'h0000_0700 , 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m7.wb_rd_mult( 32'h0000_0700 + (siz * 4), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m7.wb_wr_mult( 32'h0000_0700 + (siz * 8), 4'hf, del, siz);
- repeat(del) @(posedge clk);
- m7.wb_rd_mult( 32'h0000_0700 + (siz * 12), 4'hf, del, siz);
- t[7] = $time;
- end
-
- join
-
- verify(0,0,siz*4);
- verify(1,0,siz*4);
- verify(2,0,siz*4);
- verify(3,0,siz*4);
- verify(4,0,siz*4);
- verify(5,0,siz*4);
- verify(6,0,siz*4);
- verify(7,0,siz*4);
-
- for(a=0;a<8;a=a+1)
- for(b=0;b<8;b=b+1)
- if((t[a] < t[b]) & (p[a] <= p[b]) & (p[a] != p[b]) )
- begin
- $display("ERROR: Master %0d compleated before Master %0d", a, b);
- $display(" M[%0d] pri: %0d (t: %0t)", a, p[a], t[a]);
- $display(" M[%0d] pri: %0d (t: %0t)", b, p[b], t[b]);
- error_cnt = error_cnt + 1;
- end
- end
-
- show_errors;
- $display("*****************************************************");
- $display("*** Test DONE ... ***");
- $display("*****************************************************\n\n");
-
-end
-endtask
-
-
-
-task test_dp1;
-
-integer n;
-reg [3:0] s, s1, s2, s3, s4, s5, s6, s7;
-
-begin
-
- $display("\n\n");
- $display("*****************************************************");
- $display("*** Datapath 1 Test ... ***");
- $display("*****************************************************\n");
-
-s = 0;
-
-for(n=0;n<8;n=n+1)
- begin
- init_all_mem;
- $display("Mode: %0d", n);
-
- begin
- m0.wb_wr_mult( 32'h0000_0000 + (s << 28), 4'hf, 0, 4);
- m0.wb_rd_mult( 32'h0000_0010 + (s << 28), 4'hf, 0, 4);
- m0.wb_wr_mult( 32'h0000_0020 + (s << 28), 4'hf, 0, 4);
- m0.wb_rd_mult( 32'h0000_0030 + (s << 28), 4'hf, 0, 4);
- end
-
- begin
- m1.wb_wr_mult( 32'h0000_0100 + (s << 28), 4'hf, 0, 4);
- m1.wb_rd_mult( 32'h0000_0110 + (s << 28), 4'hf, 0, 4);
- m1.wb_wr_mult( 32'h0000_0120 + (s << 28), 4'hf, 0, 4);
- m1.wb_rd_mult( 32'h0000_0130 + (s << 28), 4'hf, 0, 4);
- end
-
- begin
- m2.wb_wr_mult( 32'h0000_0200 + (s << 28), 4'hf, 0, 4);
- m2.wb_rd_mult( 32'h0000_0210 + (s << 28), 4'hf, 0, 4);
- m2.wb_wr_mult( 32'h0000_0220 + (s << 28), 4'hf, 0, 4);
- m2.wb_rd_mult( 32'h0000_0230 + (s << 28), 4'hf, 0, 4);
- end
-
- begin
- m3.wb_wr_mult( 32'h0000_0300 + (s << 28), 4'hf, 0, 4);
- m3.wb_rd_mult( 32'h0000_0310 + (s << 28), 4'hf, 0, 4);
- m3.wb_wr_mult( 32'h0000_0320 + (s << 28), 4'hf, 0, 4);
- m3.wb_rd_mult( 32'h0000_0330 + (s << 28), 4'hf, 0, 4);
- end
-
- begin
- m4.wb_wr_mult( 32'h0000_0400 + (s << 28), 4'hf, 0, 4);
- m4.wb_rd_mult( 32'h0000_0410 + (s << 28), 4'hf, 0, 4);
- m4.wb_wr_mult( 32'h0000_0420 + (s << 28), 4'hf, 0, 4);
- m4.wb_rd_mult( 32'h0000_0430 + (s << 28), 4'hf, 0, 4);
- end
-
- begin
- m5.wb_wr_mult( 32'h0000_0500 + (s << 28), 4'hf, 0, 4);
- m5.wb_rd_mult( 32'h0000_0510 + (s << 28), 4'hf, 0, 4);
- m5.wb_wr_mult( 32'h0000_0520 + (s << 28), 4'hf, 0, 4);
- m5.wb_rd_mult( 32'h0000_0530 + (s << 28), 4'hf, 0, 4);
- end
-
- begin
- m6.wb_wr_mult( 32'h0000_0600 + (s << 28), 4'hf, 0, 4);
- m6.wb_rd_mult( 32'h0000_0610 + (s << 28), 4'hf, 0, 4);
- m6.wb_wr_mult( 32'h0000_0620 + (s << 28), 4'hf, 0, 4);
- m6.wb_rd_mult( 32'h0000_0630 + (s << 28), 4'hf, 0, 4);
- end
-
- begin
- m7.wb_wr_mult( 32'h0000_0700 + (s << 28), 4'hf, 0, 4);
- m7.wb_rd_mult( 32'h0000_0710 + (s << 28), 4'hf, 0, 4);
- m7.wb_wr_mult( 32'h0000_0720 + (s << 28), 4'hf, 0, 4);
- m7.wb_rd_mult( 32'h0000_0730 + (s << 28), 4'hf, 0, 4);
- end
-
-
- verify(0,s,16);
- verify(1,s,16);
- verify(2,s,16);
- verify(3,s,16);
- verify(4,s,16);
- verify(5,s,16);
- verify(6,s,16);
- verify(7,s,16);
-
- @(posedge clk);
-
- s = s + 1;
-// s1 = s1 + 1;
-// s2 = s2 + 1;
-// s3 = s3 + 1;
-// s4 = s4 - 1;
-// s5 = s5 - 1;
-// s6 = s6 - 1;
-// s7 = s7 - 1;
-
- @(posedge clk);
-
- end
-
- show_errors;
- $display("*****************************************************");
- $display("*** Test DONE ... ***");
- $display("*****************************************************\n\n");
-
-end
-endtask
-
-task test_dp2;
-
-integer del;
-integer x0, x1, x2, x3, x4, x5, x6, x7;
-reg [3:0] m;
-
-begin
-
- $display("\n\n");
- $display("*****************************************************");
- $display("*** Datapath 2 Test ... ***");
- $display("*****************************************************\n");
-
-del=0;
-for(del=0;del<5;del=del+1)
- begin
- init_all_mem;
- $display("Delay: %0d", del);
-
-// fork
-
- begin
- for(x0=0;x0<8;x0=x0+1)
- m0.wb_rd_mult( 32'h0000_0000 + ((0+x0) << 28) + (x0<<4), 4'hf, del, 4);
- end
-
- begin
- for(x1=0;x1<8;x1=x1+1)
- m1.wb_rd_mult( 32'h0000_0100 + ((0+x1) << 28) + (x1<<4), 4'hf, del, 4);
- end
-
- begin
- for(x2=0;x2<8;x2=x2+1)
- m2.wb_rd_mult( 32'h0000_0200 + ((0+x2) << 28) + (x2<<4), 4'hf, del, 4);
-
- end
-
- begin
- for(x3=0;x3<8;x3=x3+1)
- m3.wb_rd_mult( 32'h0000_0300 + ((0+x3) << 28) + (x3<<4), 4'hf, del, 4);
- end
-
- begin
- for(x4=0;x4<8;x4=x4+1)
- m4.wb_rd_mult( 32'h0000_0400 + ((0+x4) << 28) + (x4<<4), 4'hf, del, 4);
- end
-
- begin
- for(x5=0;x5<8;x5=x5+1)
- m5.wb_rd_mult( 32'h0000_0500 + ((0+x5) << 28) + (x5<<4), 4'hf, del, 4);
- end
-
- begin
- for(x6=0;x6<8;x6=x6+1)
- m6.wb_rd_mult( 32'h0000_0600 + ((0+x6) << 28) + (x6<<4), 4'hf, del, 4);
- end
-
- begin
- for(x7=0;x7<8;x7=x7+1)
- m7.wb_rd_mult( 32'h0000_0700 + ((0+x7) << 28) + (x7<<4), 4'hf, del, 4);
- end
-// join
-
- for(x1=0;x1<8;x1=x1+1)
- for(x0=0;x0<8;x0=x0+1)
- begin
-// m = x0+x1;
- verify_sub(x1,x0,4,(x0*4),(x0*4));
- end
-
- end
-
- show_errors;
- $display("*****************************************************");
- $display("*** Test DONE ... ***");
- $display("*****************************************************\n\n");
-
-end
-endtask
-
-
-task test_rf;
-
-integer n, m;
-reg [31:0] wdata[0:15];
-reg [31:0] rdata[0:15];
-reg [15:0] rtmp, wtmp;
-
-begin
-
- $display("\n\n");
- $display("*****************************************************");
- $display("*** Register File Test ... ***");
- $display("*****************************************************\n");
-
-for(m=0;m<5;m=m+1)
- begin
- $display("Mode: %0d", m);
-
- for(n=0;n<16;n=n+1)
- wdata[n] = $random;
-
- for(n=0;n<16;n=n+1)
- case(m)
- 0: m0.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
- 1: m3.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
- 2: m5.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
- 3: m7.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
- 4: m7.wb_wr1(32'hff00_0000 + (n << 2), 4'hf, wdata[n]);
- endcase
-
- for(n=0;n<16;n=n+1)
- case(m)
- 0: m7.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
- 1: m3.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
- 2: m6.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
- 3: m0.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
- 4: m7.wb_rd1(32'hff00_0000 + (n << 2), 4'hf, rdata[n]);
- endcase
-
- for(n=0;n<16;n=n+1)
- begin
- rtmp = rdata[n];
- wtmp = wdata[n];
- if(rtmp !== wtmp)
- begin
- $display("ERROR: RF[%0d] Mismatch. Expected: %h, Got: %h (%0t)",
- n, wtmp, rtmp, $time);
- end
- end
- end
-
- show_errors;
- $display("*****************************************************");
- $display("*** Test DONE ... ***");
- $display("*****************************************************\n\n");
-
-
-end
-endtask
-
diff --git a/opencores/wb_conbus/bench/verilog/wb_mast_model.v b/opencores/wb_conbus/bench/verilog/wb_mast_model.v
deleted file mode 100644
index e383f8290..000000000
--- a/opencores/wb_conbus/bench/verilog/wb_mast_model.v
+++ /dev/null
@@ -1,693 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// WISHBONE Master Model ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: wb_mast_model.v,v 1.1.1.1 2003/04/19 08:40:15 johny Exp $
-//
-// $Date: 2003/04/19 08:40:15 $
-// $Revision: 1.1.1.1 $
-// $Author: johny $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: wb_mast_model.v,v $
-// Revision 1.1.1.1 2003/04/19 08:40:15 johny
-// no message
-//
-// Revision 1.2 2002/10/03 05:40:03 rudi
-// Fixed a minor bug in parameter passing, updated headers and specification.
-//
-// Revision 1.1.1.1 2001/10/19 11:04:23 rudi
-// WISHBONE CONMAX IP Core
-//
-//
-//
-//
-//
-
-`include "wb_model_defines.v"
-
-module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
-
-input clk, rst;
-output [31:0] adr;
-input [31:0] din;
-output [31:0] dout;
-output cyc, stb;
-output [3:0] sel;
-output we;
-input ack, err, rty;
-
-////////////////////////////////////////////////////////////////////
-//
-// Local Wires
-//
-
-parameter mem_size = 4096;
-
-reg [31:0] adr;
-reg [31:0] dout;
-reg cyc, stb;
-reg [3:0] sel;
-reg we;
-
-reg [31:0] mem[mem_size:0];
-integer cnt;
-
-////////////////////////////////////////////////////////////////////
-//
-// Memory Logic
-//
-
-initial
- begin
- //adr = 32'hxxxx_xxxx;
- //adr = 0;
- adr = 32'hffff_ffff;
- dout = 32'hxxxx_xxxx;
- cyc = 0;
- stb = 0;
- sel = 4'hx;
- we = 1'hx;
- cnt = 0;
- #1;
- $display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
- end
-
-
-
-task mem_fill;
-
-integer n;
-begin
-cnt = 0;
-cnt = 0;
-for(n=0;n<mem_size;n=n+1)
- begin
- mem[n] = $random;
- end
-end
-endtask
-
-////////////////////////////////////////////////////////////////////
-//
-// Write 1 Word Task
-//
-
-task wb_wr1;
-input [31:0] a;
-input [3:0] s;
-input [31:0] d;
-
-begin
-
-//@(posedge clk);
-#1;
-adr = a;
-dout = d;
-cyc = 1;
-stb = 1;
-we=1;
-sel = s;
-
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-#1;
-cyc=0;
-stb=0;
-adr = 32'hxxxx_xxxx;
-//adr = 32'hffff_ffff;
-//adr = 0;
-dout = 32'hxxxx_xxxx;
-we = 1'hx;
-sel = 4'hx;
-adr = $random;
-
-end
-endtask
-
-////////////////////////////////////////////////////////////////////
-//
-// Write 4 Words Task
-//
-
-task wb_wr4;
-input [31:0] a;
-input [3:0] s;
-input delay;
-input [31:0] d1;
-input [31:0] d2;
-input [31:0] d3;
-input [31:0] d4;
-
-integer delay;
-
-begin
-
-@(posedge clk);
-#1;
-cyc = 1;
-sel = s;
-
-adr = $random;
-repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
-adr = a;
-dout = d1;
-stb = 1;
-we=1;
-while(~ack & ~err) @(posedge clk);
-#2;
-stb=0;
-we=1'bx;
-dout = 32'hxxxx_xxxx;
-adr = $random;
-
-
-repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
-stb=1;
-adr = a+4;
-dout = d2;
-we=1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-#2;
-stb=0;
-we=1'bx;
-dout = 32'hxxxx_xxxx;
-
-repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
-stb=1;
-adr = a+8;
-dout = d3;
-we=1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-#2;
-stb=0;
-we=1'bx;
-dout = 32'hxxxx_xxxx;
-adr = $random;
-
-repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
-stb=1;
-adr = a+12;
-dout = d4;
-we=1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-#1;
-stb=0;
-cyc=0;
-
-adr = 32'hxxxx_xxxx;
-adr = $random;
-//adr = 0;
-//adr = 32'hffff_ffff;
-dout = 32'hxxxx_xxxx;
-we = 1'hx;
-sel = 4'hx;
-
-end
-endtask
-
-
-task wb_wr_mult;
-input [31:0] a;
-input [3:0] s;
-input delay;
-input count;
-
-integer delay;
-integer count;
-integer n;
-
-begin
-
-//@(posedge clk);
-#1;
-cyc = 1;
-adr = $random;
-for(n=0;n<count;n=n+1)
- begin
- repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
- adr = a + (n*4);
- dout = mem[n + cnt];
- stb = 1;
- we=1;
- sel = s;
- if(n!=0) @(posedge clk);
- while(~ack & ~err) @(posedge clk);
- #2;
- stb=0;
- we=1'bx;
- sel = 4'hx;
- dout = 32'hxxxx_xxxx;
- //adr = 32'hxxxx_xxxx;
- adr = $random;
- end
-
-cyc=0;
-
-adr = 32'hxxxx_xxxx;
-//adr = 32'hffff_ffff;
-
-cnt = cnt + count;
-end
-endtask
-
-
-task wb_rmw;
-input [31:0] a;
-input [3:0] s;
-input delay;
-input rcount;
-input wcount;
-
-integer delay;
-integer rcount;
-integer wcount;
-integer n;
-
-begin
-
-@(posedge clk);
-#1;
-cyc = 1;
-we = 0;
-sel = s;
-repeat(delay) @(posedge clk);
-
-for(n=0;n<rcount-1;n=n+1)
- begin
- adr = a + (n*4);
- stb = 1;
- while(~ack & ~err) @(posedge clk);
- mem[n + cnt] = din;
- //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
- #2;
- stb=0;
- we = 1'hx;
- sel = 4'hx;
- adr = 32'hxxxx_xxxx;
- repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
- we = 0;
- sel = s;
- end
-
-adr = a+(n*4);
-stb = 1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-mem[n + cnt] = din;
-//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
-#1;
-stb=0;
-we = 1'hx;
-sel = 4'hx;
-adr = 32'hxxxx_xxxx;
-
-cnt = cnt + rcount;
-
-//@(posedge clk);
-
-
-for(n=0;n<wcount;n=n+1)
- begin
- repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
- adr = a + (n*4);
- dout = mem[n + cnt];
- stb = 1;
- we=1;
- sel = s;
-// if(n!=0)
- @(posedge clk);
- while(~ack & ~err) @(posedge clk);
- #2;
- stb=0;
- we=1'bx;
- sel = 4'hx;
- dout = 32'hxxxx_xxxx;
- adr = 32'hxxxx_xxxx;
- end
-
-cyc=0;
-
-adr = 32'hxxxx_xxxx;
-//adr = 32'hffff_ffff;
-
-cnt = cnt + wcount;
-end
-endtask
-
-
-
-
-task wb_wmr;
-input [31:0] a;
-input [3:0] s;
-input delay;
-input rcount;
-input wcount;
-
-integer delay;
-integer rcount;
-integer wcount;
-integer n;
-
-begin
-
-@(posedge clk);
-#1;
-cyc = 1;
-we = 1'bx;
-sel = 4'hx;
-sel = s;
-
-for(n=0;n<wcount;n=n+1)
- begin
- repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
- adr = a + (n*4);
- dout = mem[n + cnt];
- stb = 1;
- we=1;
- sel = s;
- @(posedge clk);
- while(~ack & ~err) @(posedge clk);
- #2;
- stb=0;
- we=1'bx;
- sel = 4'hx;
- dout = 32'hxxxx_xxxx;
- adr = 32'hxxxx_xxxx;
- end
-
-cnt = cnt + wcount;
-stb=0;
-repeat(delay) @(posedge clk);
-#1;
-
-sel = s;
-we = 0;
-for(n=0;n<rcount-1;n=n+1)
- begin
- adr = a + (n*4);
- stb = 1;
- while(~ack & ~err) @(posedge clk);
- mem[n + cnt] = din;
- //$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
- #2;
- stb=0;
- we = 1'hx;
- sel = 4'hx;
- adr = 32'hxxxx_xxxx;
- repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
- we = 0;
- sel = s;
- end
-
-adr = a+(n*4);
-stb = 1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-mem[n + cnt] = din;
-cnt = cnt + rcount;
-//$display("Rd Mem[%0d]: %h", (n + cnt), mem[n + cnt] );
-#1;
-
-cyc = 0;
-stb = 0;
-we = 1'hx;
-sel = 4'hx;
-adr = 32'hxxxx_xxxx;
-
-end
-endtask
-
-
-
-
-////////////////////////////////////////////////////////////////////
-//
-// Read 1 Word Task
-//
-
-task wb_rd1;
-input [31:0] a;
-input [3:0] s;
-output [31:0] d;
-
-begin
-
-//@(posedge clk);
-#1;
-adr = a;
-cyc = 1;
-stb = 1;
-we = 0;
-sel = s;
-
-//@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-d = din;
-#1;
-cyc=0;
-stb=0;
-//adr = 32'hxxxx_xxxx;
-//adr = 0;
-adr = 32'hffff_ffff;
-dout = 32'hxxxx_xxxx;
-we = 1'hx;
-sel = 4'hx;
-adr = $random;
-
-end
-endtask
-
-
-////////////////////////////////////////////////////////////////////
-//
-// Read 4 Words Task
-//
-
-
-task wb_rd4;
-input [31:0] a;
-input [3:0] s;
-input delay;
-output [31:0] d1;
-output [31:0] d2;
-output [31:0] d3;
-output [31:0] d4;
-
-integer delay;
-begin
-
-@(posedge clk);
-#1;
-cyc = 1;
-we = 0;
-adr = $random;
-sel = s;
-repeat(delay) @(posedge clk);
-
-adr = a;
-stb = 1;
-while(~ack & ~err) @(posedge clk);
-d1 = din;
-#2;
-stb=0;
-we = 1'hx;
-sel = 4'hx;
-adr = $random;
-repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
-we = 0;
-sel = s;
-
-adr = a+4;
-stb = 1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-d2 = din;
-#2;
-stb=0;
-we = 1'hx;
-sel = 4'hx;
-adr = $random;
-repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
-we = 0;
-sel = s;
-
-
-adr = a+8;
-stb = 1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-d3 = din;
-#2;
-stb=0;
-we = 1'hx;
-sel = 4'hx;
-adr = $random;
-repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
-we = 0;
-sel = s;
-
-adr = a+12;
-stb = 1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-d4 = din;
-#1;
-stb=0;
-cyc=0;
-we = 1'hx;
-sel = 4'hx;
-adr = 32'hffff_ffff;
-adr = $random;
-end
-endtask
-
-
-
-task wb_rd_mult;
-input [31:0] a;
-input [3:0] s;
-input delay;
-input count;
-
-integer delay;
-integer count;
-integer n;
-
-begin
-
-//@(posedge clk);
-#1;
-cyc = 1;
-we = 0;
-sel = s;
-repeat(delay) @(posedge clk);
-
-for(n=0;n<count-1;n=n+1)
- begin
- adr = a + (n*4);
- stb = 1;
- while(~ack & ~err) @(posedge clk);
- mem[n + cnt] = din;
- #2;
- stb=0;
- we = 1'hx;
- sel = 4'hx;
- //adr = 32'hxxxx_xxxx;
- adr = $random;
- repeat(delay)
- begin
- @(posedge clk);
- #1;
- end
- we = 0;
- sel = s;
- end
-
-adr = a+(n*4);
-stb = 1;
-@(posedge clk);
-while(~ack & ~err) @(posedge clk);
-mem[n + cnt] = din;
-#1;
-stb=0;
-cyc=0;
-we = 1'hx;
-sel = 4'hx;
-//adr = 32'hffff_ffff;
-//adr = 32'hxxxx_xxxx;
-adr = $random;
-
-cnt = cnt + count;
-end
-endtask
-
-endmodule
diff --git a/opencores/wb_conbus/bench/verilog/wb_model_defines.v b/opencores/wb_conbus/bench/verilog/wb_model_defines.v
deleted file mode 100644
index 1dba91c42..000000000
--- a/opencores/wb_conbus/bench/verilog/wb_model_defines.v
+++ /dev/null
@@ -1,64 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// WISHBONE Model Definitions ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: wb_model_defines.v,v 1.1.1.1 2003/04/19 08:40:16 johny Exp $
-//
-// $Date: 2003/04/19 08:40:16 $
-// $Revision: 1.1.1.1 $
-// $Author: johny $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: wb_model_defines.v,v $
-// Revision 1.1.1.1 2003/04/19 08:40:16 johny
-// no message
-//
-// Revision 1.2 2002/10/03 05:40:03 rudi
-// Fixed a minor bug in parameter passing, updated headers and specification.
-//
-// Revision 1.1.1.1 2001/10/19 11:04:23 rudi
-// WISHBONE CONMAX IP Core
-//
-//
-//
-//
-//
-//
-
-`timescale 1ns / 10ps
diff --git a/opencores/wb_conbus/bench/verilog/wb_slv_model.v b/opencores/wb_conbus/bench/verilog/wb_slv_model.v
deleted file mode 100644
index f58001aad..000000000
--- a/opencores/wb_conbus/bench/verilog/wb_slv_model.v
+++ /dev/null
@@ -1,167 +0,0 @@
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// WISHBONE Slave Model ////
-//// ////
-//// ////
-//// Author: Rudolf Usselmann ////
-//// rudi@asics.ws ////
-//// ////
-//// ////
-//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000-2002 Rudolf Usselmann ////
-//// www.asics.ws ////
-//// rudi@asics.ws ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer.////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-// CVS Log
-//
-// $Id: wb_slv_model.v,v 1.1.1.1 2003/04/19 08:40:16 johny Exp $
-//
-// $Date: 2003/04/19 08:40:16 $
-// $Revision: 1.1.1.1 $
-// $Author: johny $
-// $Locker: $
-// $State: Exp $
-//
-// Change History:
-// $Log: wb_slv_model.v,v $
-// Revision 1.1.1.1 2003/04/19 08:40:16 johny
-// no message
-//
-// Revision 1.2 2002/10/03 05:40:03 rudi
-// Fixed a minor bug in parameter passing, updated headers and specification.
-//
-// Revision 1.1.1.1 2001/10/19 11:04:25 rudi
-// WISHBONE CONMAX IP Core
-//
-// Revision 1.1 2001/07/29 08:57:02 rudi
-//
-//
-// 1) Changed Directory Structure
-// 2) Added restart signal (REST)
-//
-// Revision 1.1.1.1 2001/03/19 13:11:29 rudi
-// Initial Release
-//
-//
-//
-
-`include "wb_model_defines.v"
-
-module wb_slv(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
-
-input clk, rst;
-input [31:0] adr, din;
-output [31:0] dout;
-input cyc, stb;
-input [3:0] sel;
-input we;
-output ack, err, rty;
-
-////////////////////////////////////////////////////////////////////
-//
-// Local Wires
-//
-
-parameter mem_size = 13;
-parameter sz = (1<<mem_size)-1;
-
-reg [31:0] mem[sz:0];
-wire mem_re, mem_we;
-wire [31:0] tmp;
-reg [31:0] dout, tmp2;
-
-reg err, rty;
-reg [31:0] del_ack;
-reg [5:0] delay;
-
-////////////////////////////////////////////////////////////////////
-//
-// Memory Logic
-//
-
-initial
- begin
- delay = 0;
- err = 0;
- rty = 0;
- #2;
- $display("\nINFO: WISHBONE MEMORY MODEL INSTANTIATED (%m)");
- $display(" Memory Size %0d address lines %0d words\n",
- mem_size, sz+1);
- end
-
-assign mem_re = cyc & stb & !we;
-assign mem_we = cyc & stb & we;
-
-assign tmp = mem[adr[mem_size+1:2]];
-
-always @(sel or tmp or mem_re or ack)
- if(mem_re & ack)
- begin
- dout[31:24] <= #1 sel[3] ? tmp[31:24] : 8'hxx;
- dout[23:16] <= #1 sel[2] ? tmp[23:16] : 8'hxx;
- dout[15:08] <= #1 sel[1] ? tmp[15:08] : 8'hxx;
- dout[07:00] <= #1 sel[0] ? tmp[07:00] : 8'hxx;
- end
- else dout <= #1 32'hzzzz_zzzz;
-
-
-always @(sel or tmp or din)
- begin
- tmp2[31:24] = !sel[3] ? tmp[31:24] : din[31:24];
- tmp2[23:16] = !sel[2] ? tmp[23:16] : din[23:16];
- tmp2[15:08] = !sel[1] ? tmp[15:08] : din[15:08];
- tmp2[07:00] = !sel[0] ? tmp[07:00] : din[07:00];
- end
-
-always @(posedge clk)
- if(mem_we) mem[adr[mem_size+1:2]] <= #1 tmp2;
-
-always @(posedge clk)
- del_ack = ack ? 0 : {del_ack[30:0], (mem_re | mem_we)};
-
-assign #1 ack = cyc & ((delay==0) ? (mem_re | mem_we) : del_ack[delay-1]);
-
-task fill_mem;
-input mode;
-
-integer n, mode;
-
-begin
-
-for(n=0;n<(sz+1);n=n+1)
- begin
- case(mode)
- 0: mem[n] = { ~n[15:0], n[15:0] };
- 1: mem[n] = $random;
- endcase
- end
-
-end
-endtask
-
-endmodule
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