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| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
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| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /opencores/uart16550/sim/rtl_sim/bin | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'opencores/uart16550/sim/rtl_sim/bin')
| -rw-r--r-- | opencores/uart16550/sim/rtl_sim/bin/CVS/Entries | 3 | ||||
| -rw-r--r-- | opencores/uart16550/sim/rtl_sim/bin/CVS/Repository | 1 | ||||
| -rw-r--r-- | opencores/uart16550/sim/rtl_sim/bin/CVS/Root | 1 | ||||
| -rw-r--r-- | opencores/uart16550/sim/rtl_sim/bin/CVS/Template | 0 | ||||
| -rw-r--r-- | opencores/uart16550/sim/rtl_sim/bin/nc.scr | 9 | ||||
| -rw-r--r-- | opencores/uart16550/sim/rtl_sim/bin/sim.tcl | 5 |
6 files changed, 19 insertions, 0 deletions
diff --git a/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries b/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries new file mode 100644 index 000000000..4993d601c --- /dev/null +++ b/opencores/uart16550/sim/rtl_sim/bin/CVS/Entries @@ -0,0 +1,3 @@ +/nc.scr/1.4/Mon Jul 29 21:15:18 2002/-kb/ +/sim.tcl/1.2/Mon Dec 3 21:44:29 2001/-kb/ +D diff --git a/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository b/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository new file mode 100644 index 000000000..1ea808f7b --- /dev/null +++ b/opencores/uart16550/sim/rtl_sim/bin/CVS/Repository @@ -0,0 +1 @@ +uart16550/sim/rtl_sim/bin diff --git a/opencores/uart16550/sim/rtl_sim/bin/CVS/Root b/opencores/uart16550/sim/rtl_sim/bin/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/uart16550/sim/rtl_sim/bin/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/sim/rtl_sim/bin/CVS/Template b/opencores/uart16550/sim/rtl_sim/bin/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/uart16550/sim/rtl_sim/bin/CVS/Template diff --git a/opencores/uart16550/sim/rtl_sim/bin/nc.scr b/opencores/uart16550/sim/rtl_sim/bin/nc.scr new file mode 100644 index 000000000..c42e3c346 --- /dev/null +++ b/opencores/uart16550/sim/rtl_sim/bin/nc.scr @@ -0,0 +1,9 @@ ++libext+.v ++access+wr ++mess ++incdir+../../../rtl/verilog+../../../bench/verilog ++tcl+../bin/sim.tcl +-y ../../../rtl/verilog +-y ../../../bench/verilog +../../../bench/verilog/uart_test.v +//+gui diff --git a/opencores/uart16550/sim/rtl_sim/bin/sim.tcl b/opencores/uart16550/sim/rtl_sim/bin/sim.tcl new file mode 100644 index 000000000..18a0dbec4 --- /dev/null +++ b/opencores/uart16550/sim/rtl_sim/bin/sim.tcl @@ -0,0 +1,5 @@ +database -open waves -into ../out/uart -default +probe -create -shm uart_test -all -depth all +stop -create -time 1000000000ns -relative +run +quit |