diff options
| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /opencores/uart16550/rtl/verilog/CVS | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'opencores/uart16550/rtl/verilog/CVS')
| -rw-r--r-- | opencores/uart16550/rtl/verilog/CVS/Entries | 13 | ||||
| -rw-r--r-- | opencores/uart16550/rtl/verilog/CVS/Repository | 1 | ||||
| -rw-r--r-- | opencores/uart16550/rtl/verilog/CVS/Root | 1 | ||||
| -rw-r--r-- | opencores/uart16550/rtl/verilog/CVS/Template | 0 |
4 files changed, 15 insertions, 0 deletions
diff --git a/opencores/uart16550/rtl/verilog/CVS/Entries b/opencores/uart16550/rtl/verilog/CVS/Entries new file mode 100644 index 000000000..924308393 --- /dev/null +++ b/opencores/uart16550/rtl/verilog/CVS/Entries @@ -0,0 +1,13 @@ +/raminfr.v/1.2/Mon Jul 29 21:16:18 2002// +/timescale.v/1.6/Fri Aug 24 21:01:12 2001// +/uart_debug_if.v/1.5/Mon Jul 29 21:16:18 2002// +/uart_defines.v/1.14/Fri Sep 12 07:26:58 2003// +/uart_receiver.v/1.31/Fri Jun 18 14:46:15 2004// +/uart_regs.v/1.42/Mon Nov 22 09:21:59 2004// +/uart_rfifo.v/1.4/Fri Jul 11 18:20:26 2003// +/uart_sync_flops.v/1.1/Fri May 21 11:43:25 2004// +/uart_tfifo.v/1.2/Mon Jul 29 21:16:18 2002// +/uart_top.v/1.19/Mon Jul 29 21:16:18 2002// +/uart_transmitter.v/1.19/Mon Jul 29 21:16:18 2002// +/uart_wb.v/1.17/Fri May 21 12:35:15 2004// +D diff --git a/opencores/uart16550/rtl/verilog/CVS/Repository b/opencores/uart16550/rtl/verilog/CVS/Repository new file mode 100644 index 000000000..b0efc9dbb --- /dev/null +++ b/opencores/uart16550/rtl/verilog/CVS/Repository @@ -0,0 +1 @@ +uart16550/rtl/verilog diff --git a/opencores/uart16550/rtl/verilog/CVS/Root b/opencores/uart16550/rtl/verilog/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/uart16550/rtl/verilog/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/uart16550/rtl/verilog/CVS/Template b/opencores/uart16550/rtl/verilog/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/uart16550/rtl/verilog/CVS/Template |