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| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /opencores/sd_interface/syn | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'opencores/sd_interface/syn')
| -rw-r--r-- | opencores/sd_interface/syn/spiMaster.qpf | 23 | ||||
| -rw-r--r-- | opencores/sd_interface/syn/spiMaster.qsf | 57 |
2 files changed, 80 insertions, 0 deletions
diff --git a/opencores/sd_interface/syn/spiMaster.qpf b/opencores/sd_interface/syn/spiMaster.qpf new file mode 100644 index 000000000..f60b6c834 --- /dev/null +++ b/opencores/sd_interface/syn/spiMaster.qpf @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "7.2"
+DATE = "14:03:18 February 21, 2008"
+
+
+# Revisions
+
+PROJECT_REVISION = "spiMaster"
diff --git a/opencores/sd_interface/syn/spiMaster.qsf b/opencores/sd_interface/syn/spiMaster.qsf new file mode 100644 index 000000000..3a5f88801 --- /dev/null +++ b/opencores/sd_interface/syn/spiMaster.qsf @@ -0,0 +1,57 @@ +# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+# spiMaster_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+# assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY spiMaster
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:03:18 FEBRUARY 21, 2008"
+set_global_assignment -name LAST_QUARTUS_VERSION 7.2
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name DEVICE_FILTER_PACKAGE PQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBus_h.v
+set_global_assignment -name VERILOG_FILE ../rtl/ctrlStsRegBI.v
+set_global_assignment -name VERILOG_FILE ../rtl/dpMem_dc.v
+set_global_assignment -name VERILOG_FILE ../rtl/fifoRTL.v
+set_global_assignment -name VERILOG_FILE ../rtl/initSD.v
+set_global_assignment -name VERILOG_FILE ../rtl/readWriteSDBlock.v
+set_global_assignment -name VERILOG_FILE ../rtl/readWriteSPIWireData.v
+set_global_assignment -name VERILOG_FILE ../rtl/RxFifo.v
+set_global_assignment -name VERILOG_FILE ../rtl/RxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../rtl/sendCmd.v
+set_global_assignment -name VERILOG_FILE ../rtl/spiCtrl.v
+set_global_assignment -name VERILOG_FILE ../rtl/spiMaster.v
+set_global_assignment -name VERILOG_FILE ../rtl/spiMaster_h.v
+set_global_assignment -name VERILOG_FILE ../rtl/spiTxRxData.v
+set_global_assignment -name VERILOG_FILE ../rtl/timescale.v
+set_global_assignment -name VERILOG_FILE ../rtl/TxFifo.v
+set_global_assignment -name VERILOG_FILE ../rtl/TxFifoBI.v
+set_global_assignment -name VERILOG_FILE ../rtl/wishBoneBI.v
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
\ No newline at end of file |