diff options
| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:00:25 -0700 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:07:59 -0700 |
| commit | 1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (patch) | |
| tree | 04f94ef4f7f06a210f7532592829332c7f2621f0 /opencores/sd_interface/sim/testHarness | |
| parent | 7b8f65256b5ea300187ebb6a359df2fa707a295d (diff) | |
| parent | 42fc55415af499980901c7787f44c7e74b4a9ce1 (diff) | |
| download | uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.gz uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.bz2 uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.zip | |
Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
...
Diffstat (limited to 'opencores/sd_interface/sim/testHarness')
| -rw-r--r-- | opencores/sd_interface/sim/testHarness | 5458 |
1 files changed, 0 insertions, 5458 deletions
diff --git a/opencores/sd_interface/sim/testHarness b/opencores/sd_interface/sim/testHarness deleted file mode 100644 index 08c4dad3c..000000000 --- a/opencores/sd_interface/sim/testHarness +++ /dev/null @@ -1,5458 +0,0 @@ -:vpi_time_precision - 12;
-:vpi_module "system";
-S_005FC090 .scope module, "testCase0" "testCase0";
- .timescale -9;
-V_$006AD848 .var "dataRead", 7, 0;
-V_$006AFD38 .var "dataWrite", 7, 0;
-V_$006AFE40 .var/i "i", 31, 0;
-S_006338F0 .scope module, "testHarness" "testHarness";
- .timescale -9;
-V_$006E2EF0 .net "ack", 0, 0, V_$006DE038[0];
-V_$006E2F60 .net "adr", 7, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7];
-V_$006DF4B8 .var "clk", 0, 0;
-V_$006DF480 .net "masterDin", 7, 0, V_$006DE8E8[0], V_$006DE8E8[1], V_$006DE8E8[2], V_$006DE8E8[3], V_$006DE8E8[4], V_$006DE8E8[5], V_$006DE8E8[6], V_$006DE8E8[7];
-V_$006E31C0 .net "masterDout", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006E0BD0 .var "rst", 0, 0;
-V_$006E0D70 .net "spiCS_n", 0, 0, L_006E3660;
-V_$006DE750 .net "spiClk", 0, 0, V_$006CAA28[0];
-V_$006DE7C0 .net "spiMasterDataIn", 0, 0, V_$00644A08[0];
-V_$006E3498 .net "spiMasterDataOut", 0, 0, V_$006CAAD8[0];
-V_$006E3508 .var "spiSysClk", 0, 0;
-V_$006E3578 .net "stb", 0, 0, V_$006607B0[0];
-V_$006E35B0 .net "we", 0, 0, V_$006A5C98[0];
-S_006C1500 .scope module, "u_spiMasterTop" "spiMasterTop", S_006338F0;
- .timescale -9;
-L_006E3540 .functor AND, V_$006DADF8[0], V_$006D6C70[0], C<1>, C<1>;
-L_006E3660 .functor AND, L_006E3540, V_$006DBBB8[0], C<1>, C<1>;
-V_$006DDD50 .net "SDAddr", 31, 0, V_$006DBED8[0], V_$006DBED8[1], V_$006DBED8[2], V_$006DBED8[3], V_$006DBED8[4], V_$006DBED8[5], V_$006DBED8[6], V_$006DBED8[7], V_$006DBED8[8], V_$006DBED8[9], V_$006DBED8[10], V_$006DBED8[11], V_$006DBED8[12], V_$006DBED8[13], V_$006DBED8[14], V_$006DBED8[15], V_$006DBED8[16], V_$006DBED8[17], V_$006DBED8[18], V_$006DBED8[19], V_$006DBED8[20], V_$006DBED8[21], V_$006DBED8[22], V_$006DBED8[23], V_$006DBED8[24], V_$006DBED8[25], V_$006DBED8[26], V_$006DBED8[27], V_$006DBED8[28], V_$006DBED8[29], V_$006DBED8[30], V_$006DBED8[31];
-V_$006DF148 .net "SDInitError", 1, 0, V_$006D8260[0], V_$006D8260[1];
-V_$006DF1E0 .net "SDReadError", 1, 0, V_$006D6488[0], V_$006D6488[1];
-V_$006DF278 .net "SDWriteError", 1, 0, V_$006D75E8[0], V_$006D75E8[1];
-V_$006DF310 .net "ack_o", 0, 0, V_$006DE038[0];
-V_$006DF378 .net "address_i", 7, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7];
-V_$006DF4F0 .net "checkSumByteFromInitSD", 7, 0, V_$006D7F80[0], V_$006D7F80[1], V_$006D7F80[2], V_$006D7F80[3], V_$006D7F80[4], V_$006D7F80[5], V_$006D7F80[6], V_$006D7F80[7];
-V_$006DF608 .net "checkSumByteFromRWSDBlock", 7, 0, V_$006D2790[0], V_$006D2790[1], V_$006D2790[2], V_$006D2790[3], V_$006D2790[4], V_$006D2790[5], V_$006D2790[6], V_$006D2790[7];
-V_$006DF7E8 .net "clk_i", 0, 0, V_$006DF4B8[0];
-V_$006DF850 .net "cmdByteFromInitSD", 7, 0, V_$006D7B08[0], V_$006D7B08[1], V_$006D7B08[2], V_$006D7B08[3], V_$006D7B08[4], V_$006D7B08[5], V_$006D7B08[6], V_$006D7B08[7];
-V_$006DFA08 .net "cmdByteFromRWSDBlock", 7, 0, V_$006D2970[0], V_$006D2970[1], V_$006D2970[2], V_$006D2970[3], V_$006D2970[4], V_$006D2970[5], V_$006D2970[6], V_$006D2970[7];
-V_$006DFBF0 .net "dataByte1FromInitSD", 7, 0, V_$006D7C70[0], V_$006D7C70[1], V_$006D7C70[2], V_$006D7C70[3], V_$006D7C70[4], V_$006D7C70[5], V_$006D7C70[6], V_$006D7C70[7];
-V_$006DFDD0 .net "dataByte1FromRWSDBlock", 7, 0, V_$006D2AB0[0], V_$006D2AB0[1], V_$006D2AB0[2], V_$006D2AB0[3], V_$006D2AB0[4], V_$006D2AB0[5], V_$006D2AB0[6], V_$006D2AB0[7];
-V_$006DFA40 .net "dataByte2FromInitSD", 7, 0, V_$006D7DD0[0], V_$006D7DD0[1], V_$006D7DD0[2], V_$006D7DD0[3], V_$006D7DD0[4], V_$006D7DD0[5], V_$006D7DD0[6], V_$006D7DD0[7];
-V_$006D8068 .net "dataByte2FromRWSDBlock", 7, 0, V_$006D2C18[0], V_$006D2C18[1], V_$006D2C18[2], V_$006D2C18[3], V_$006D2C18[4], V_$006D2C18[5], V_$006D2C18[6], V_$006D2C18[7];
-V_$006D2D38 .net "dataByte3FromInitSD", 7, 0, V_$006D80C8[0], V_$006D80C8[1], V_$006D80C8[2], V_$006D80C8[3], V_$006D80C8[4], V_$006D80C8[5], V_$006D80C8[6], V_$006D80C8[7];
-V_$006D81E8 .net "dataByte3FromRWSDBlock", 7, 0, V_$006D2D78[0], V_$006D2D78[1], V_$006D2D78[2], V_$006D2D78[3], V_$006D2D78[4], V_$006D2D78[5], V_$006D2D78[6], V_$006D2D78[7];
-V_$006D30F8 .net "dataByte4FromInitSD", 7, 0, V_$006D8228[0], V_$006D8228[1], V_$006D8228[2], V_$006D8228[3], V_$006D8228[4], V_$006D8228[5], V_$006D8228[6], V_$006D8228[7];
-V_$006D8380 .net "dataByte4FromRWSDBlock", 7, 0, V_$006D3138[0], V_$006D3138[1], V_$006D3138[2], V_$006D3138[3], V_$006D3138[4], V_$006D3138[5], V_$006D3138[6], V_$006D3138[7];
-V_$006E0468 .net "dataFromCtrlStsReg", 7, 0, V_$006DC658[0], V_$006DC658[1], V_$006DC658[2], V_$006DC658[3], V_$006DC658[4], V_$006DC658[5], V_$006DC658[6], V_$006DC658[7];
-V_$006E0590 .net "dataFromRxFifo", 7, 0, V_$006A5290[0], V_$006A5290[1], V_$006A5290[2], V_$006A5290[3], V_$006A5290[4], V_$006A5290[5], V_$006A5290[6], V_$006A5290[7];
-V_$006E07B0 .net "dataFromTxFifo", 7, 0, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>;
-V_$006E09D0 .net "data_i", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006DE808 .net "data_o", 7, 0, V_$006DE8E8[0], V_$006DE8E8[1], V_$006DE8E8[2], V_$006DE8E8[3], V_$006DE8E8[4], V_$006DE8E8[5], V_$006DE8E8[6], V_$006DE8E8[7];
-V_$006DE868 .net "readWriteSDBlockReq", 1, 0, V_$006DBA28[0], V_$006DBA28[1];
-V_$006DE8A0 .net "rstSyncToSpiClk", 0, 0, V_$006DCA00[0];
-V_$006E0D38 .net "rst_i", 0, 0, V_$006E0BD0[0];
-V_$006E0DA8 .net "rxDataFromRWSPIWireData", 7, 0, V_$006C90B8[0], V_$006C90B8[1], V_$006C90B8[2], V_$006C90B8[3], V_$006C90B8[4], V_$006C90B8[5], V_$006C90B8[6], V_$006C90B8[7];
-V_$006CB650 .net "rxDataFromSpiTxRxData", 7, 0, V_$006CB750[0], V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6], V_$006CB750[7];
-V_$006DD040 .net "rxDataRdyClrFromRWSDBlock", 0, 0, V_$006D6920[0];
-V_$006DD008 .net "rxDataRdyClrFromSendCmd", 0, 0, V_$006D1308[0];
-V_$006DCD68 .net "rxDataRdySetFromRWSPIWireData", 0, 0, V_$006CA688[0];
-V_$006DCD30 .net "rxFifoDataIn", 7, 0, V_$006D6958[0], V_$006D6958[1], V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5], V_$006D6958[6], V_$006D6958[7];
-V_$006D6B58 .net "sendCmdRespByte", 7, 0, V_$006D0B40[0], V_$006D0B40[1], V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4], V_$006D0B40[5], V_$006D0B40[6], V_$006D0B40[7];
-V_$006DCCC0 .net "spiCS_n", 0, 0, L_006E3660;
-V_$006DCC88 .net "spiCS_nFromInitSD", 0, 0, V_$006DADF8[0];
-V_$006DCC50 .net "spiCS_nFromRWSDBlock", 0, 0, V_$006D6C70[0];
-V_$006E12C8 .net "spiCS_nFromSpiCtrl", 0, 0, V_$006DBBB8[0];
-V_$006E1300 .net "spiClkDelayFromCtrlStsReg", 7, 0, V_$006DCA38[0], V_$006DCA38[1], V_$006DCA38[2], V_$006DCA38[3], V_$006DCA38[4], V_$006DCA38[5], V_$006DCA38[6], V_$006DCA38[7];
-V_$006DCB70 .net "spiClkDelayFromInitSD", 7, 0, V_$006DB188[0], V_$006DB188[1], V_$006DB188[2], V_$006DB188[3], V_$006DB188[4], V_$006DB188[5], V_$006DB188[6], V_$006DB188[7];
-V_$006DB2A8 .net "spiClkOut", 0, 0, V_$006CAA28[0];
-V_$006E1450 .net "spiDataIn", 0, 0, V_$00644A08[0];
-V_$006E14B8 .net "spiDataOut", 0, 0, V_$006CAAD8[0];
-V_$006E1520 .net "spiDirectAccessTxData", 7, 0, V_$006DD220[0], V_$006DD220[1], V_$006DD220[2], V_$006DD220[3], V_$006DD220[4], V_$006DD220[5], V_$006DD220[6], V_$006DD220[7];
-V_$006DD340 .net "spiSysClk", 0, 0, V_$006E3508[0];
-V_$006E1700 .net "spiTransType", 1, 0, V_$006DDBA0[0], V_$006DDBA0[1];
-V_$006DDBD8 .net "strobe_i", 0, 0, V_$006607B0[0];
-V_$006E1798 .net "txDataFromInitSD", 7, 0, V_$006D71D0[0], V_$006D71D0[1], V_$006D71D0[2], V_$006D71D0[3], V_$006D71D0[4], V_$006D71D0[5], V_$006D71D0[6], V_$006D71D0[7];
-V_$006DB478 .net "txDataFromRWSDBlock", 7, 0, V_$006D7208[0], V_$006D7208[1], V_$006D7208[2], V_$006D7208[3], V_$006D7208[4], V_$006D7208[5], V_$006D7208[6], V_$006D7208[7];
-V_$006D7268 .net "txDataFromSendCmd", 7, 0, V_$006D1678[0], V_$006D1678[1], V_$006D1678[2], V_$006D1678[3], V_$006D1678[4], V_$006D1678[5], V_$006D1678[6], V_$006D1678[7];
-V_$006E1AE8 .net "txDataFullClrFromRWSPIWireData", 0, 0, V_$006CAC78[0];
-V_$006E1B50 .net "txDataFullFromSpiTxRxData", 0, 0, V_$006CC7A8[0];
-V_$006E1B88 .net "txDataToRWSPIWireData", 7, 0, V_$006CC858[0], V_$006CC858[1], V_$006CC858[2], V_$006CC858[3], V_$006CC858[4], V_$006CC858[5], V_$006CC858[6], V_$006CC858[7];
-V_$006CC978 .net "txDataWenFromInitSD", 0, 0, V_$006DB4B8[0];
-V_$006E1CD8 .net "txDataWenFromRWSDBlock", 0, 0, V_$006D72A8[0];
-V_$006E1D40 .net "txDataWenFromSendCmd", 0, 0, V_$006D17B8[0];
-V_$006E1DA8 .net "txFifoDataOut", 7, 0, V_$006C7CF0[0], V_$006C7CF0[1], V_$006C7CF0[2], V_$006C7CF0[3], V_$006C7CF0[4], V_$006C7CF0[5], V_$006C7CF0[6], V_$006C7CF0[7];
-V_$006E1FC8 .net "we_i", 0, 0, V_$006A5C98[0];
-V_$006E2040 .net "ctrlStsRegSel", 0, 0, V_$006DE140[0];
-V_$006E2078 .net "rxFifoSel", 0, 0, V_$006DE9B8[0];
-V_$006E20E8 .net "txFifoSel", 0, 0, V_$006DEA20[0];
-V_$006E2158 .net "spiTransCtrl", 0, 0, V_$006DDF80[0];
-V_$006E2190 .net "spiTransSts", 0, 0, V_$006DBC48[0];
-V_$006E21C8 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0];
-V_$006E2310 .net "readWriteSDBlockRdy", 0, 0, V_$006D6E38[0];
-V_$006E2348 .net "rxDataRdyFromSpiTxRxData", 0, 0, V_$006CB9B8[0];
-V_$006E2498 .net "rxDataRdyClrFromSpiCtrl", 0, 0, V_$006DAC70[0];
-V_$006E24D0 .net "SDInitRdy", 0, 0, V_$006D7E68[0];
-V_$006E2628 .net "SDInitReq", 0, 0, V_$006DB678[0];
-V_$006E2660 .net "txDataWenFromSpiCtrl", 0, 0, V_$006DBDB0[0];
-V_$006E27C0 .net "sendCmdRespTout", 0, 0, V_$006D1010[0];
-V_$006E2830 .net "rxDataRdyClrFromInitSD", 0, 0, V_$006DACA8[0];
-V_$006E2998 .net "sendCmdRdy", 0, 0, V_$006D1360[0];
-V_$006E2A08 .net "sendCmdReqFromInitSD", 0, 0, V_$006DAD18[0];
-V_$006E2B78 .net "txDataEmptyFromRWSPIWireData", 0, 0, V_$006CAB30[0];
-V_$006DB320 .net "rRxFifoWE", 0, 0, V_$006D6B90[0];
-V_$006D6BC8 .net "sendCmdReqFromRWSDBlock", 0, 0, V_$006D6C38[0];
-V_$006E2CF0 .net "txFifoRE", 0, 0, V_$006D7488[0];
-V_$006D75B0 .net "hostTxFifoEmpty", 0, 0, V_$006C7FF8[0];
-V_$006E2EB8 .net "hostRxFifoFull", 0, 0, V_$006C4260[0];
-S_006DD638 .scope module, "u_wishBoneBI" "wishBoneBI", S_006C1500;
- .timescale -9;
-V_$006DDE60 .var "ack_delayed", 0, 0;
-V_$006DDEE0 .var "ack_immediate", 0, 0;
-V_$006DE038 .var "ack_o", 0, 0;
-V_$006DE0A8 .net "address", 7, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7];
-V_$006DE108 .net "clk", 0, 0, V_$006DF4B8[0];
-V_$006DE140 .var "ctrlStsRegSel", 0, 0;
-V_$006DE178 .net "dataFromCtrlStsReg", 7, 0, V_$006DC658[0], V_$006DC658[1], V_$006DC658[2], V_$006DC658[3], V_$006DC658[4], V_$006DC658[5], V_$006DC658[6], V_$006DC658[7];
-V_$006DE280 .net "dataFromRxFifo", 7, 0, V_$006A5290[0], V_$006A5290[1], V_$006A5290[2], V_$006A5290[3], V_$006A5290[4], V_$006A5290[5], V_$006A5290[6], V_$006A5290[7];
-V_$006DE3A0 .net "dataFromTxFifo", 7, 0, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>;
-V_$006DE5B8 .net "dataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006DE8E8 .var "dataOut", 7, 0;
-V_$006DE980 .net "rst", 0, 0, V_$006E0BD0[0];
-V_$006DE9B8 .var "rxFifoSel", 0, 0;
-V_$006DE920 .net "strobe_i", 0, 0, V_$006607B0[0];
-V_$006DEA20 .var "txFifoSel", 0, 0;
-V_$006DEA88 .net "writeEn", 0, 0, V_$006A5C98[0];
-E_006DDDA0/0 .event edge, V_$006DDEE0[0], V_$006DDE60[0], V_$0068AE60[0], V_$0068AE60[1];
-E_006DDDA0/1 .event edge, V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5];
-E_006DDDA0/2 .event edge, V_$0068AE60[6], V_$0068AE60[7], V_$006A5C98[0];
-E_006DDDA0 .event/or E_006DDDA0/0, E_006DDDA0/1, E_006DDDA0/2;
-E_006DDDF8 .event edge, V_$006607B0[0];
-E_006DDE28/0 .event edge, C<0>, C<0>, C<0>, C<0>;
-E_006DDE28/1 .event edge, C<0>, C<0>, C<0>, C<0>;
-E_006DDE28/2 .event edge, V_$006A5290[0], V_$006A5290[1], V_$006A5290[2], V_$006A5290[3];
-E_006DDE28/3 .event edge, V_$006A5290[4], V_$006A5290[5], V_$006A5290[6], V_$006A5290[7];
-E_006DDE28/4 .event edge, V_$006DC658[0], V_$006DC658[1], V_$006DC658[2], V_$006DC658[3];
-E_006DDE28/5 .event edge, V_$006DC658[4], V_$006DC658[5], V_$006DC658[6], V_$006DC658[7];
-E_006DDE28/6 .event edge, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3];
-E_006DDE28/7 .event edge, V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7];
-E_006DDE28 .event/or E_006DDE28/0, E_006DDE28/1, E_006DDE28/2, E_006DDE28/3, E_006DDE28/4, E_006DDE28/5, E_006DDE28/6, E_006DDE28/7;
-S_006DBE08 .scope module, "u_ctrlStsRegBI" "ctrlStsRegBI", S_006C1500;
- .timescale -9;
-V_$006DBED8 .var "SDAddr", 31, 0;
-V_$006DC3C8 .net "SDInitError", 1, 0, V_$006D8260[0], V_$006D8260[1];
-V_$006DC440 .var "SDInitErrorSTB", 1, 0;
-V_$006DC478 .net "SDReadError", 1, 0, V_$006D6488[0], V_$006D6488[1];
-V_$006DC4D0 .var "SDReadErrorSTB", 1, 0;
-V_$006DCE08 .net "SDWriteError", 1, 0, V_$006D75E8[0], V_$006D75E8[1];
-V_$006DCE80 .var "SDWriteErrorSTB", 1, 0;
-V_$006DCEF8 .net "address", 7, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3], V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7];
-V_$006DC578 .net "busClk", 0, 0, V_$006DF4B8[0];
-V_$006DC5B0 .net "ctrlStsRegSel", 0, 0, V_$006DE140[0];
-V_$006DC5E8 .net "dataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006DC658 .var "dataOut", 7, 0;
-V_$006DC6B8 .var "rstFromBus", 0, 0;
-V_$006DC620 .net "rstFromWire", 0, 0, V_$006E0BD0[0];
-V_$006DC710 .var "rstShift", 5, 0;
-V_$006DC940 .var "rstSyncToBusClkOut", 0, 0;
-V_$006DC978 .var "rstSyncToSpiClkFirst", 0, 0;
-V_$006DCA00 .var "rstSyncToSpiClkOut", 0, 0;
-V_$006DCA38 .var "spiClkDelay", 7, 0;
-V_$006DCBF0 .net "spiDirectAccessRxData", 7, 0, V_$006CB750[0], V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6], V_$006CB750[7];
-V_$006DD078 .var "spiDirectAccessRxDataSTB", 7, 0;
-V_$006DD220 .var "spiDirectAccessTxData", 7, 0;
-V_$006DD380 .var "spiDirectAccessTxDataSTB", 7, 0;
-V_$006DDF48 .net "spiSysClk", 0, 0, V_$006E3508[0];
-V_$006DDF80 .var "spiTransCtrl", 0, 0;
-V_$006DD6A8 .var "spiTransCtrlSTB", 0, 0;
-V_$006DD6E0 .var "spiTransCtrlShift", 5, 0;
-V_$006DD918 .net "spiTransStatus", 0, 0, V_$006DBC48[0];
-V_$006DD970 .var "spiTransStatusReg1", 0, 0;
-V_$006DD9E0 .var "spiTransStatusReg2", 0, 0;
-V_$006DDAA8 .var "spiTransStatusSTB", 0, 0;
-V_$006DDBA0 .var "spiTransType", 1, 0;
-V_$006DDC18 .var "spiTransTypeSTB", 1, 0;
-V_$006DDCE0 .net "strobe_i", 0, 0, V_$006607B0[0];
-V_$006DDD18 .net "writeEn", 0, 0, V_$006A5C98[0];
-E_006DBE78/0 .event edge, V_$006DC710[0], V_$006DC710[1], V_$006DC710[2], V_$006DC710[3];
-E_006DBE78/1 .event edge, V_$006DC710[4], V_$006DC710[5];
-E_006DBE78 .event/or E_006DBE78/0, E_006DBE78/1;
-E_006DBEB8/0 .event edge, V_$006DD078[0], V_$006DD078[1], V_$006DD078[2], V_$006DD078[3];
-E_006DBEB8/1 .event edge, V_$006DD078[4], V_$006DD078[5], V_$006DD078[6], V_$006DD078[7];
-E_006DBEB8/2 .event edge, V_$006DDAA8[0], V_$006DD6A8[0], V_$006DDC18[0], V_$006DDC18[1];
-E_006DBEB8/3 .event edge, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2], V_$0068AE60[3];
-E_006DBEB8/4 .event edge, V_$0068AE60[4], V_$0068AE60[5], V_$0068AE60[6], V_$0068AE60[7];
-E_006DBEB8 .event/or E_006DBEB8/0, E_006DBEB8/1, E_006DBEB8/2, E_006DBEB8/3, E_006DBEB8/4;
-S_006DA008 .scope module, "u_spiCtrl" "spiCtrl", S_006C1500;
- .timescale -9;
-V_$006DB530 .var "CurrState_spiCtrlSt", 2, 0;
-V_$006DB5C8 .var "NextState_spiCtrlSt", 2, 0;
-V_$006DB620 .net "SDInitRdy", 0, 0, V_$006D7E68[0];
-V_$006DB678 .var "SDInitReq", 0, 0;
-V_$006DB6D0 .net "clk", 0, 0, V_$006E3508[0];
-V_$006DB728 .var "next_SDInitReq", 0, 0;
-V_$006DB760 .var "next_readWriteSDBlockReq", 1, 0;
-V_$006DB7C0 .var "next_rxDataRdyClr", 0, 0;
-V_$006DB810 .var "next_spiCS_n", 0, 0;
-V_$006DB890 .var "next_spiTransSts", 0, 0;
-V_$006DB918 .var "next_txDataWen", 0, 0;
-V_$006DB9D0 .net "readWriteSDBlockRdy", 0, 0, V_$006D6E38[0];
-V_$006DBA28 .var "readWriteSDBlockReq", 1, 0;
-V_$006DB950 .net "rst", 0, 0, V_$006DCA00[0];
-V_$006DBB18 .net "rxDataRdy", 0, 0, V_$006CB9B8[0];
-V_$006DAC70 .var "rxDataRdyClr", 0, 0;
-V_$006DBBB8 .var "spiCS_n", 0, 0;
-V_$006DBC10 .net "spiTransCtrl", 0, 0, V_$006DDF80[0];
-V_$006DBC48 .var "spiTransSts", 0, 0;
-V_$006DBCC8 .net "spiTransType", 1, 0, V_$006DDBA0[0], V_$006DDBA0[1];
-V_$006DBDB0 .var "txDataWen", 0, 0;
-E_006DB510/0 .event edge, V_$006DB530[0], V_$006DB530[1], V_$006DB530[2], V_$006DBBB8[0];
-E_006DB510/1 .event edge, V_$006DBC48[0], V_$006DAC70[0], V_$006DB678[0], V_$006DBDB0[0];
-E_006DB510/2 .event edge, V_$006DBA28[0], V_$006DBA28[1], V_$006D6E38[0], V_$006D7E68[0];
-E_006DB510/3 .event edge, V_$006CB9B8[0], V_$006DDF80[0];
-E_006DB510 .event/or E_006DB510/0, E_006DB510/1, E_006DB510/2, E_006DB510/3;
-S_006D5E10 .scope module, "u_initSD" "initSD", S_006C1500;
- .timescale -9;
-V_$006D7810 .var "CurrState_initSDSt", 3, 0;
-V_$006D78C0 .var "NextState_initSDSt", 3, 0;
-V_$006D7E68 .var "SDInitRdy", 0, 0;
-V_$006D7F00 .net "SDInitReq", 0, 0, V_$006DB678[0];
-V_$006D7F80 .var "checkSumByte", 7, 0;
-V_$006D7AD0 .net "clk", 0, 0, V_$006E3508[0];
-V_$006D7B08 .var "cmdByte", 7, 0;
-V_$006D7C70 .var "dataByte1", 7, 0;
-V_$006D7DD0 .var "dataByte2", 7, 0;
-V_$006D80C8 .var "dataByte3", 7, 0;
-V_$006D8228 .var "dataByte4", 7, 0;
-V_$006D83C0 .var "delCnt1", 9, 0;
-V_$006D83F8 .var "delCnt2", 7, 0;
-V_$006D8260 .var "initError", 1, 0;
-V_$006D8E20 .var "loopCnt", 7, 0;
-V_$006D8560 .var "next_SDInitRdy", 0, 0;
-V_$006D85E0 .var "next_checkSumByte", 7, 0;
-V_$006D8900 .var "next_cmdByte", 7, 0;
-V_$006D8B78 .var "next_dataByte1", 7, 0;
-V_$006D90D8 .var "next_dataByte2", 7, 0;
-V_$006D93B8 .var "next_dataByte3", 7, 0;
-V_$006D9F90 .var "next_dataByte4", 7, 0;
-V_$006D9750 .var "next_delCnt1", 9, 0;
-V_$006D9AB8 .var "next_delCnt2", 7, 0;
-V_$006D9D58 .var "next_initError", 1, 0;
-V_$006DA0A8 .var "next_loopCnt", 7, 0;
-V_$006DA348 .var "next_rxDataRdyClr", 0, 0;
-V_$006DA3D0 .var "next_sendCmdReq", 0, 0;
-V_$006DA450 .var "next_spiCS_n", 0, 0;
-V_$006DA4D0 .var "next_spiClkDelayOut", 7, 0;
-V_$006DA638 .var "next_txDataOut", 7, 0;
-V_$006DA918 .var "next_txDataWen", 0, 0;
-V_$006DA998 .net "respByte", 7, 0, V_$006D0B40[0], V_$006D0B40[1], V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4], V_$006D0B40[5], V_$006D0B40[6], V_$006D0B40[7];
-V_$006DAB98 .net "respTout", 0, 0, V_$006D1010[0];
-V_$006DAC00 .net "rst", 0, 0, V_$006DCA00[0];
-V_$006DAC38 .net "rxDataRdy", 0, 0, V_$006CB9B8[0];
-V_$006DACA8 .var "rxDataRdyClr", 0, 0;
-V_$006DACE0 .net "sendCmdRdy", 0, 0, V_$006D1360[0];
-V_$006DAD18 .var "sendCmdReq", 0, 0;
-V_$006DADF8 .var "spiCS_n", 0, 0;
-V_$006DAE30 .net "spiClkDelayIn", 7, 0, V_$006DCA38[0], V_$006DCA38[1], V_$006DCA38[2], V_$006DCA38[3], V_$006DCA38[4], V_$006DCA38[5], V_$006DCA38[6], V_$006DCA38[7];
-V_$006DB188 .var "spiClkDelayOut", 7, 0;
-V_$006DB2E8 .net "txDataEmpty", 0, 0, V_$006CAB30[0];
-V_$006DB358 .net "txDataFull", 0, 0, V_$006CC7A8[0];
-V_$006D71D0 .var "txDataOut", 7, 0;
-V_$006DB4B8 .var "txDataWen", 0, 0;
-E_006C8B28/0 .event edge, V_$006D7810[0], V_$006D7810[1], V_$006D7810[2], V_$006D7810[3];
-E_006C8B28/1 .event edge, V_$006DACA8[0], V_$006DAD18[0], V_$006D7F80[0], V_$006D7F80[1];
-E_006C8B28/2 .event edge, V_$006D7F80[2], V_$006D7F80[3], V_$006D7F80[4], V_$006D7F80[5];
-E_006C8B28/3 .event edge, V_$006D7F80[6], V_$006D7F80[7], V_$006D8228[0], V_$006D8228[1];
-E_006C8B28/4 .event edge, V_$006D8228[2], V_$006D8228[3], V_$006D8228[4], V_$006D8228[5];
-E_006C8B28/5 .event edge, V_$006D8228[6], V_$006D8228[7], V_$006D80C8[0], V_$006D80C8[1];
-E_006C8B28/6 .event edge, V_$006D80C8[2], V_$006D80C8[3], V_$006D80C8[4], V_$006D80C8[5];
-E_006C8B28/7 .event edge, V_$006D80C8[6], V_$006D80C8[7], V_$006D7DD0[0], V_$006D7DD0[1];
-E_006C8B28/8 .event edge, V_$006D7DD0[2], V_$006D7DD0[3], V_$006D7DD0[4], V_$006D7DD0[5];
-E_006C8B28/9 .event edge, V_$006D7DD0[6], V_$006D7DD0[7], V_$006D7C70[0], V_$006D7C70[1];
-E_006C8B28/10 .event edge, V_$006D7C70[2], V_$006D7C70[3], V_$006D7C70[4], V_$006D7C70[5];
-E_006C8B28/11 .event edge, V_$006D7C70[6], V_$006D7C70[7], V_$006D7B08[0], V_$006D7B08[1];
-E_006C8B28/12 .event edge, V_$006D7B08[2], V_$006D7B08[3], V_$006D7B08[4], V_$006D7B08[5];
-E_006C8B28/13 .event edge, V_$006D7B08[6], V_$006D7B08[7], V_$006DB4B8[0], V_$006D71D0[0];
-E_006C8B28/14 .event edge, V_$006D71D0[1], V_$006D71D0[2], V_$006D71D0[3], V_$006D71D0[4];
-E_006C8B28/15 .event edge, V_$006D71D0[5], V_$006D71D0[6], V_$006D71D0[7], V_$006D8260[0];
-E_006C8B28/16 .event edge, V_$006D8260[1], V_$006DADF8[0], V_$006D7E68[0], V_$006DB188[0];
-E_006C8B28/17 .event edge, V_$006DB188[1], V_$006DB188[2], V_$006DB188[3], V_$006DB188[4];
-E_006C8B28/18 .event edge, V_$006DB188[5], V_$006DB188[6], V_$006DB188[7], V_$006CAB30[0];
-E_006C8B28/19 .event edge, V_$006D83F8[0], V_$006D83F8[1], V_$006D83F8[2], V_$006D83F8[3];
-E_006C8B28/20 .event edge, V_$006D83F8[4], V_$006D83F8[5], V_$006D83F8[6], V_$006D83F8[7];
-E_006C8B28/21 .event edge, V_$006D83C0[0], V_$006D83C0[1], V_$006D83C0[2], V_$006D83C0[3];
-E_006C8B28/22 .event edge, V_$006D83C0[4], V_$006D83C0[5], V_$006D83C0[6], V_$006D83C0[7];
-E_006C8B28/23 .event edge, V_$006D83C0[8], V_$006D83C0[9], V_$006D0B40[0], V_$006D0B40[1];
-E_006C8B28/24 .event edge, V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4], V_$006D0B40[5];
-E_006C8B28/25 .event edge, V_$006D0B40[6], V_$006D0B40[7], V_$006D1010[0], V_$006D1360[0];
-E_006C8B28/26 .event edge, V_$006D8E20[0], V_$006D8E20[1], V_$006D8E20[2], V_$006D8E20[3];
-E_006C8B28/27 .event edge, V_$006D8E20[4], V_$006D8E20[5], V_$006D8E20[6], V_$006D8E20[7];
-E_006C8B28/28 .event edge, V_$006CC7A8[0], V_$006DB678[0], V_$006DCA38[0], V_$006DCA38[1];
-E_006C8B28/29 .event edge, V_$006DCA38[2], V_$006DCA38[3], V_$006DCA38[4], V_$006DCA38[5];
-E_006C8B28/30 .event edge, V_$006DCA38[6], V_$006DCA38[7];
-E_006C8B28 .event/or E_006C8B28/0, E_006C8B28/1, E_006C8B28/2, E_006C8B28/3, E_006C8B28/4, E_006C8B28/5, E_006C8B28/6, E_006C8B28/7, E_006C8B28/8, E_006C8B28/9, E_006C8B28/10, E_006C8B28/11, E_006C8B28/12, E_006C8B28/13, E_006C8B28/14, E_006C8B28/15, E_006C8B28/16, E_006C8B28/17, E_006C8B28/18, E_006C8B28/19, E_006C8B28/20, E_006C8B28/21, E_006C8B28/22, E_006C8B28/23, E_006C8B28/24, E_006C8B28/25, E_006C8B28/26, E_006C8B28/27, E_006C8B28/28, E_006C8B28/29, E_006C8B28/30;
-S_006D0E50 .scope module, "u_readWriteSDBlock" "readWriteSDBlock", S_006C1500;
- .timescale -9;
-V_$006D1830 .var "CurrState_rwBlkSt", 5, 0;
-V_$006D1C70 .var "NextState_rwBlkSt", 5, 0;
-V_$006D2078 .net "blockAddr", 31, 0, V_$006DBED8[0], V_$006DBED8[1], V_$006DBED8[2], V_$006DBED8[3], V_$006DBED8[4], V_$006DBED8[5], V_$006DBED8[6], V_$006DBED8[7], V_$006DBED8[8], V_$006DBED8[9], V_$006DBED8[10], V_$006DBED8[11], V_$006DBED8[12], V_$006DBED8[13], V_$006DBED8[14], V_$006DBED8[15], V_$006DBED8[16], V_$006DBED8[17], V_$006DBED8[18], V_$006DBED8[19], V_$006DBED8[20], V_$006DBED8[21], V_$006DBED8[22], V_$006DBED8[23], V_$006DBED8[24], V_$006DBED8[25], V_$006DBED8[26], V_$006DBED8[27], V_$006DBED8[28], V_$006DBED8[29], V_$006DBED8[30], V_$006DBED8[31];
-V_$006D2790 .var "checkSumByte", 7, 0;
-V_$006D28F0 .net "clk", 0, 0, V_$006E3508[0];
-V_$006D2970 .var "cmdByte", 7, 0;
-V_$006D2AB0 .var "dataByte1", 7, 0;
-V_$006D2C18 .var "dataByte2", 7, 0;
-V_$006D2D78 .var "dataByte3", 7, 0;
-V_$006D3138 .var "dataByte4", 7, 0;
-V_$006D3278 .var "delCnt1", 7, 0;
-V_$006D3310 .var "delCnt2", 7, 0;
-V_$006D3370 .var "locRespByte", 7, 0;
-V_$006D32B0 .var "loopCnt", 8, 0;
-V_$006D3580 .var "next_checkSumByte", 7, 0;
-V_$006D3890 .var "next_cmdByte", 7, 0;
-V_$006D3B18 .var "next_dataByte1", 7, 0;
-V_$006D40D8 .var "next_dataByte2", 7, 0;
-V_$006D43B8 .var "next_dataByte3", 7, 0;
-V_$006D4F90 .var "next_dataByte4", 7, 0;
-V_$006D4750 .var "next_delCnt1", 7, 0;
-V_$006D4A70 .var "next_delCnt2", 7, 0;
-V_$006D4D10 .var "next_locRespByte", 7, 0;
-V_$006D5200 .var "next_loopCnt", 8, 0;
-V_$006D5DD8 .var "next_readError", 1, 0;
-V_$006D5F20 .var "next_readWriteSDBlockRdy", 0, 0;
-V_$006D5FB0 .var "next_rxDataRdyClr", 0, 0;
-V_$006D5520 .var "next_rxFifoData", 7, 0;
-V_$006D5800 .var "next_rxFifoWen", 0, 0;
-V_$006D5880 .var "next_sendCmdReq", 0, 0;
-V_$006D5948 .var "next_spiCS_n", 0, 0;
-V_$006D5A20 .var "next_timeOutCnt", 9, 0;
-V_$006D6008 .var "next_txDataOut", 7, 0;
-V_$006D62B0 .var "next_txDataWen", 0, 0;
-V_$006D6330 .var "next_txFifoRen", 0, 0;
-V_$006D63B0 .var "next_writeError", 1, 0;
-V_$006D6488 .var "readError", 1, 0;
-V_$006D6E38 .var "readWriteSDBlockRdy", 0, 0;
-V_$006D6EC0 .net "readWriteSDBlockReq", 1, 0, V_$006DBA28[0], V_$006DBA28[1];
-V_$006D6F98 .net "respByte", 7, 0, V_$006D0B40[0], V_$006D0B40[1], V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4], V_$006D0B40[5], V_$006D0B40[6], V_$006D0B40[7];
-V_$006D6648 .net "respTout", 0, 0, V_$006D1010[0];
-V_$006D66A0 .net "rst", 0, 0, V_$006DCA00[0];
-V_$006D66D8 .net "rxDataIn", 7, 0, V_$006CB750[0], V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6], V_$006CB750[7];
-V_$006D68B8 .net "rxDataRdy", 0, 0, V_$006CB9B8[0];
-V_$006D6920 .var "rxDataRdyClr", 0, 0;
-V_$006D6958 .var "rxFifoData", 7, 0;
-V_$006D6B90 .var "rxFifoWen", 0, 0;
-V_$006D6C00 .net "sendCmdRdy", 0, 0, V_$006D1360[0];
-V_$006D6C38 .var "sendCmdReq", 0, 0;
-V_$006D6C70 .var "spiCS_n", 0, 0;
-V_$006D6CA8 .var "timeOutCnt", 9, 0;
-V_$006D7160 .net "txDataEmpty", 0, 0, V_$006CAB30[0];
-V_$006D7198 .net "txDataFull", 0, 0, V_$006CC7A8[0];
-V_$006D7208 .var "txDataOut", 7, 0;
-V_$006D72A8 .var "txDataWen", 0, 0;
-V_$006D73E8 .net "txFifoData", 7, 0, V_$006C7CF0[0], V_$006C7CF0[1], V_$006C7CF0[2], V_$006C7CF0[3], V_$006C7CF0[4], V_$006C7CF0[5], V_$006C7CF0[6], V_$006C7CF0[7];
-V_$006D7488 .var "txFifoRen", 0, 0;
-V_$006D75E8 .var "writeError", 1, 0;
-E_006D1810/0 .event edge, V_$006D1830[0], V_$006D1830[1], V_$006D1830[2], V_$006D1830[3];
-E_006D1810/1 .event edge, V_$006D1830[4], V_$006D1830[5], V_$006D6958[0], V_$006D6958[1];
-E_006D1810/2 .event edge, V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5];
-E_006D1810/3 .event edge, V_$006D6958[6], V_$006D6958[7], V_$006D6B90[0], V_$006D7488[0];
-E_006D1810/4 .event edge, V_$006D6C38[0], V_$006D2790[0], V_$006D2790[1], V_$006D2790[2];
-E_006D1810/5 .event edge, V_$006D2790[3], V_$006D2790[4], V_$006D2790[5], V_$006D2790[6];
-E_006D1810/6 .event edge, V_$006D2790[7], V_$006D3138[0], V_$006D3138[1], V_$006D3138[2];
-E_006D1810/7 .event edge, V_$006D3138[3], V_$006D3138[4], V_$006D3138[5], V_$006D3138[6];
-E_006D1810/8 .event edge, V_$006D3138[7], V_$006D2D78[0], V_$006D2D78[1], V_$006D2D78[2];
-E_006D1810/9 .event edge, V_$006D2D78[3], V_$006D2D78[4], V_$006D2D78[5], V_$006D2D78[6];
-E_006D1810/10 .event edge, V_$006D2D78[7], V_$006D2C18[0], V_$006D2C18[1], V_$006D2C18[2];
-E_006D1810/11 .event edge, V_$006D2C18[3], V_$006D2C18[4], V_$006D2C18[5], V_$006D2C18[6];
-E_006D1810/12 .event edge, V_$006D2C18[7], V_$006D2AB0[0], V_$006D2AB0[1], V_$006D2AB0[2];
-E_006D1810/13 .event edge, V_$006D2AB0[3], V_$006D2AB0[4], V_$006D2AB0[5], V_$006D2AB0[6];
-E_006D1810/14 .event edge, V_$006D2AB0[7], V_$006D2970[0], V_$006D2970[1], V_$006D2970[2];
-E_006D1810/15 .event edge, V_$006D2970[3], V_$006D2970[4], V_$006D2970[5], V_$006D2970[6];
-E_006D1810/16 .event edge, V_$006D2970[7], V_$006D6920[0], V_$006D72A8[0], V_$006D7208[0];
-E_006D1810/17 .event edge, V_$006D7208[1], V_$006D7208[2], V_$006D7208[3], V_$006D7208[4];
-E_006D1810/18 .event edge, V_$006D7208[5], V_$006D7208[6], V_$006D7208[7], V_$006D75E8[0];
-E_006D1810/19 .event edge, V_$006D75E8[1], V_$006D6488[0], V_$006D6488[1], V_$006D6C70[0];
-E_006D1810/20 .event edge, V_$006D6E38[0], V_$006D3310[0], V_$006D3310[1], V_$006D3310[2];
-E_006D1810/21 .event edge, V_$006D3310[3], V_$006D3310[4], V_$006D3310[5], V_$006D3310[6];
-E_006D1810/22 .event edge, V_$006D3310[7], V_$006D3278[0], V_$006D3278[1], V_$006D3278[2];
-E_006D1810/23 .event edge, V_$006D3278[3], V_$006D3278[4], V_$006D3278[5], V_$006D3278[6];
-E_006D1810/24 .event edge, V_$006D3278[7], V_$006CB750[0], V_$006CB750[1], V_$006CB750[2];
-E_006D1810/25 .event edge, V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6];
-E_006D1810/26 .event edge, V_$006CB750[7], V_$006CB9B8[0], V_$006D3370[0], V_$006D3370[1];
-E_006D1810/27 .event edge, V_$006D3370[2], V_$006D3370[3], V_$006D3370[4], V_$006D3370[5];
-E_006D1810/28 .event edge, V_$006D3370[6], V_$006D3370[7], V_$006D6CA8[0], V_$006D6CA8[1];
-E_006D1810/29 .event edge, V_$006D6CA8[2], V_$006D6CA8[3], V_$006D6CA8[4], V_$006D6CA8[5];
-E_006D1810/30 .event edge, V_$006D6CA8[6], V_$006D6CA8[7], V_$006D6CA8[8], V_$006D6CA8[9];
-E_006D1810/31 .event edge, V_$006CAB30[0], V_$006C7CF0[0], V_$006C7CF0[1], V_$006C7CF0[2];
-E_006D1810/32 .event edge, V_$006C7CF0[3], V_$006C7CF0[4], V_$006C7CF0[5], V_$006C7CF0[6];
-E_006D1810/33 .event edge, V_$006C7CF0[7], V_$006D32B0[0], V_$006D32B0[1], V_$006D32B0[2];
-E_006D1810/34 .event edge, V_$006D32B0[3], V_$006D32B0[4], V_$006D32B0[5], V_$006D32B0[6];
-E_006D1810/35 .event edge, V_$006D32B0[7], V_$006D32B0[8], V_$006CC7A8[0], V_$006DBA28[0];
-E_006D1810/36 .event edge, V_$006DBA28[1], V_$006D1360[0], V_$006DBED8[0], V_$006DBED8[1];
-E_006D1810/37 .event edge, V_$006DBED8[2], V_$006DBED8[3], V_$006DBED8[4], V_$006DBED8[5];
-E_006D1810/38 .event edge, V_$006DBED8[6], V_$006DBED8[7], V_$006DBED8[8], V_$006DBED8[9];
-E_006D1810/39 .event edge, V_$006DBED8[10], V_$006DBED8[11], V_$006DBED8[12], V_$006DBED8[13];
-E_006D1810/40 .event edge, V_$006DBED8[14], V_$006DBED8[15], V_$006DBED8[16], V_$006DBED8[17];
-E_006D1810/41 .event edge, V_$006DBED8[18], V_$006DBED8[19], V_$006DBED8[20], V_$006DBED8[21];
-E_006D1810/42 .event edge, V_$006DBED8[22], V_$006DBED8[23], V_$006DBED8[24], V_$006DBED8[25];
-E_006D1810/43 .event edge, V_$006DBED8[26], V_$006DBED8[27], V_$006DBED8[28], V_$006DBED8[29];
-E_006D1810/44 .event edge, V_$006DBED8[30], V_$006DBED8[31];
-E_006D1810 .event/or E_006D1810/0, E_006D1810/1, E_006D1810/2, E_006D1810/3, E_006D1810/4, E_006D1810/5, E_006D1810/6, E_006D1810/7, E_006D1810/8, E_006D1810/9, E_006D1810/10, E_006D1810/11, E_006D1810/12, E_006D1810/13, E_006D1810/14, E_006D1810/15, E_006D1810/16, E_006D1810/17, E_006D1810/18, E_006D1810/19, E_006D1810/20, E_006D1810/21, E_006D1810/22, E_006D1810/23, E_006D1810/24, E_006D1810/25, E_006D1810/26, E_006D1810/27, E_006D1810/28, E_006D1810/29, E_006D1810/30, E_006D1810/31, E_006D1810/32, E_006D1810/33, E_006D1810/34, E_006D1810/35, E_006D1810/36, E_006D1810/37, E_006D1810/38, E_006D1810/39, E_006D1810/40, E_006D1810/41, E_006D1810/42, E_006D1810/43, E_006D1810/44;
-S_006CC9E8 .scope module, "u_sendCmd" "sendCmd", S_006C1500;
- .timescale -9;
-V_$006CCC20 .var "CurrState_sndCmdSt", 4, 0;
-V_$006CCD78 .var "NextState_sndCmdSt", 4, 0;
-V_$006CD0D8 .var "checkSumByte", 7, 0;
-V_$006CD390 .net "checkSumByte_1", 7, 0, V_$006D7F80[0], V_$006D7F80[1], V_$006D7F80[2], V_$006D7F80[3], V_$006D7F80[4], V_$006D7F80[5], V_$006D7F80[6], V_$006D7F80[7];
-V_$006CDF58 .net "checkSumByte_2", 7, 0, V_$006D2790[0], V_$006D2790[1], V_$006D2790[2], V_$006D2790[3], V_$006D2790[4], V_$006D2790[5], V_$006D2790[6], V_$006D2790[7];
-V_$006CD750 .net "clk", 0, 0, V_$006E3508[0];
-V_$006CD788 .var "cmdByte", 7, 0;
-V_$006CDA58 .net "cmdByte_1", 7, 0, V_$006D7B08[0], V_$006D7B08[1], V_$006D7B08[2], V_$006D7B08[3], V_$006D7B08[4], V_$006D7B08[5], V_$006D7B08[6], V_$006D7B08[7];
-V_$006CDCF8 .net "cmdByte_2", 7, 0, V_$006D2970[0], V_$006D2970[1], V_$006D2970[2], V_$006D2970[3], V_$006D2970[4], V_$006D2970[5], V_$006D2970[6], V_$006D2970[7];
-V_$006CE188 .var "dataByte1", 7, 0;
-V_$006CE428 .net "dataByte1_1", 7, 0, V_$006D7C70[0], V_$006D7C70[1], V_$006D7C70[2], V_$006D7C70[3], V_$006D7C70[4], V_$006D7C70[5], V_$006D7C70[6], V_$006D7C70[7];
-V_$006CE538 .net "dataByte1_2", 7, 0, V_$006D2AB0[0], V_$006D2AB0[1], V_$006D2AB0[2], V_$006D2AB0[3], V_$006D2AB0[4], V_$006D2AB0[5], V_$006D2AB0[6], V_$006D2AB0[7];
-V_$006CE7B0 .var "dataByte2", 7, 0;
-V_$006CE460 .net "dataByte2_1", 7, 0, V_$006D7DD0[0], V_$006D7DD0[1], V_$006D7DD0[2], V_$006D7DD0[3], V_$006D7DD0[4], V_$006D7DD0[5], V_$006D7DD0[6], V_$006D7DD0[7];
-V_$006CECD8 .net "dataByte2_2", 7, 0, V_$006D2C18[0], V_$006D2C18[1], V_$006D2C18[2], V_$006D2C18[3], V_$006D2C18[4], V_$006D2C18[5], V_$006D2C18[6], V_$006D2C18[7];
-V_$006CF158 .var "dataByte3", 7, 0;
-V_$006CF3F8 .net "dataByte3_1", 7, 0, V_$006D80C8[0], V_$006D80C8[1], V_$006D80C8[2], V_$006D80C8[3], V_$006D80C8[4], V_$006D80C8[5], V_$006D80C8[6], V_$006D80C8[7];
-V_$006CFF80 .net "dataByte3_2", 7, 0, V_$006D2D78[0], V_$006D2D78[1], V_$006D2D78[2], V_$006D2D78[3], V_$006D2D78[4], V_$006D2D78[5], V_$006D2D78[6], V_$006D2D78[7];
-V_$006CF750 .var "dataByte4", 7, 0;
-V_$006CFA18 .net "dataByte4_1", 7, 0, V_$006D8228[0], V_$006D8228[1], V_$006D8228[2], V_$006D8228[3], V_$006D8228[4], V_$006D8228[5], V_$006D8228[6], V_$006D8228[7];
-V_$006CFCB8 .net "dataByte4_2", 7, 0, V_$006D3138[0], V_$006D3138[1], V_$006D3138[2], V_$006D3138[3], V_$006D3138[4], V_$006D3138[5], V_$006D3138[6], V_$006D3138[7];
-V_$006D01A8 .var "next_respByte", 7, 0;
-V_$006D0488 .var "next_respTout", 0, 0;
-V_$006D04F0 .var "next_rxDataRdyClr", 0, 0;
-V_$006D0E18 .var "next_sendCmdRdy", 0, 0;
-V_$006D0F08 .var "next_timeOutCnt", 9, 0;
-V_$006D07C0 .var "next_txDataOut", 7, 0;
-V_$006D0AC0 .var "next_txDataWen", 0, 0;
-V_$006D0B40 .var "respByte", 7, 0;
-V_$006D1010 .var "respTout", 0, 0;
-V_$006D1090 .net "rst", 0, 0, V_$006DCA00[0];
-V_$006D1150 .net "rxDataIn", 7, 0, V_$006CB750[0], V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4], V_$006CB750[5], V_$006CB750[6], V_$006CB750[7];
-V_$006D12B0 .net "rxDataRdy", 0, 0, V_$006CB9B8[0];
-V_$006D1308 .var "rxDataRdyClr", 0, 0;
-V_$006D1360 .var "sendCmdRdy", 0, 0;
-V_$006D1398 .var "sendCmdReq", 0, 0;
-V_$006D13D0 .net "sendCmdReq1", 0, 0, V_$006DAD18[0];
-V_$006D1428 .net "sendCmdReq2", 0, 0, V_$006D6C38[0];
-V_$006D14A8 .var "timeOutCnt", 9, 0;
-V_$006D15B8 .net "txDataEmpty", 0, 0, V_$006CAB30[0];
-V_$006D1610 .net "txDataFull", 0, 0, V_$006CC7A8[0];
-V_$006D1678 .var "txDataOut", 7, 0;
-V_$006D17B8 .var "txDataWen", 0, 0;
-E_006CCA58/0 .event edge, V_$006CCC20[0], V_$006CCC20[1], V_$006CCC20[2], V_$006CCC20[3];
-E_006CCA58/1 .event edge, V_$006CCC20[4], V_$006D1360[0], V_$006D1010[0], V_$006D1308[0];
-E_006CCA58/2 .event edge, V_$006D1678[0], V_$006D1678[1], V_$006D1678[2], V_$006D1678[3];
-E_006CCA58/3 .event edge, V_$006D1678[4], V_$006D1678[5], V_$006D1678[6], V_$006D1678[7];
-E_006CCA58/4 .event edge, V_$006D17B8[0], V_$006D1398[0], V_$006CD788[0], V_$006CD788[1];
-E_006CCA58/5 .event edge, V_$006CD788[2], V_$006CD788[3], V_$006CD788[4], V_$006CD788[5];
-E_006CCA58/6 .event edge, V_$006CD788[6], V_$006CD788[7], V_$006CD0D8[0], V_$006CD0D8[1];
-E_006CCA58/7 .event edge, V_$006CD0D8[2], V_$006CD0D8[3], V_$006CD0D8[4], V_$006CD0D8[5];
-E_006CCA58/8 .event edge, V_$006CD0D8[6], V_$006CD0D8[7], V_$006CAB30[0], V_$006CF750[0];
-E_006CCA58/9 .event edge, V_$006CF750[1], V_$006CF750[2], V_$006CF750[3], V_$006CF750[4];
-E_006CCA58/10 .event edge, V_$006CF750[5], V_$006CF750[6], V_$006CF750[7], V_$006CF158[0];
-E_006CCA58/11 .event edge, V_$006CF158[1], V_$006CF158[2], V_$006CF158[3], V_$006CF158[4];
-E_006CCA58/12 .event edge, V_$006CF158[5], V_$006CF158[6], V_$006CF158[7], V_$006CE188[0];
-E_006CCA58/13 .event edge, V_$006CE188[1], V_$006CE188[2], V_$006CE188[3], V_$006CE188[4];
-E_006CCA58/14 .event edge, V_$006CE188[5], V_$006CE188[6], V_$006CE188[7], V_$006D0B40[0];
-E_006CCA58/15 .event edge, V_$006D0B40[1], V_$006D0B40[2], V_$006D0B40[3], V_$006D0B40[4];
-E_006CCA58/16 .event edge, V_$006D0B40[5], V_$006D0B40[6], V_$006D0B40[7], V_$006CB750[0];
-E_006CCA58/17 .event edge, V_$006CB750[1], V_$006CB750[2], V_$006CB750[3], V_$006CB750[4];
-E_006CCA58/18 .event edge, V_$006CB750[5], V_$006CB750[6], V_$006CB750[7], V_$006CB9B8[0];
-E_006CCA58/19 .event edge, V_$006D14A8[0], V_$006D14A8[1], V_$006D14A8[2], V_$006D14A8[3];
-E_006CCA58/20 .event edge, V_$006D14A8[4], V_$006D14A8[5], V_$006D14A8[6], V_$006D14A8[7];
-E_006CCA58/21 .event edge, V_$006D14A8[8], V_$006D14A8[9], V_$006CE7B0[0], V_$006CE7B0[1];
-E_006CCA58/22 .event edge, V_$006CE7B0[2], V_$006CE7B0[3], V_$006CE7B0[4], V_$006CE7B0[5];
-E_006CCA58/23 .event edge, V_$006CE7B0[6], V_$006CE7B0[7], V_$006CC7A8[0];
-E_006CCA58 .event/or E_006CCA58/0, E_006CCA58/1, E_006CCA58/2, E_006CCA58/3, E_006CCA58/4, E_006CCA58/5, E_006CCA58/6, E_006CCA58/7, E_006CCA58/8, E_006CCA58/9, E_006CCA58/10, E_006CCA58/11, E_006CCA58/12, E_006CCA58/13, E_006CCA58/14, E_006CCA58/15, E_006CCA58/16, E_006CCA58/17, E_006CCA58/18, E_006CCA58/19, E_006CCA58/20, E_006CCA58/21, E_006CCA58/22, E_006CCA58/23;
-E_006CCC00 .event edge, V_$006D6C38[0], V_$006DAD18[0];
-S_006CABC8 .scope module, "u_spiTxRxData" "spiTxRxData", S_006C1500;
- .timescale -9;
-V_$006CBE48 .net "clk", 0, 0, V_$006E3508[0];
-V_$006CBE80 .net "rst", 0, 0, V_$006DCA00[0];
-V_$006CBEB8 .net "rx1DataRdyClr", 0, 0, V_$006D6920[0];
-V_$006CBF60 .net "rx2DataRdyClr", 0, 0, V_$006D1308[0];
-V_$006CB4F8 .net "rx3DataRdyClr", 0, 0, V_$006DACA8[0];
-V_$006CB568 .net "rx4DataRdyClr", 0, 0, V_$006DAC70[0];
-V_$006CB5F0 .net "rxDataIn", 7, 0, V_$006C90B8[0], V_$006C90B8[1], V_$006C90B8[2], V_$006C90B8[3], V_$006C90B8[4], V_$006C90B8[5], V_$006C90B8[6], V_$006C90B8[7];
-V_$006CB750 .var "rxDataOut", 7, 0;
-V_$006CB9B8 .var "rxDataRdy", 0, 0;
-V_$006CBA20 .net "rxDataRdySet", 0, 0, V_$006CA688[0];
-V_$006CBA78 .net "tx1DataIn", 7, 0, V_$006D7208[0], V_$006D7208[1], V_$006D7208[2], V_$006D7208[3], V_$006D7208[4], V_$006D7208[5], V_$006D7208[6], V_$006D7208[7];
-V_$006CBD38 .net "tx1DataWEn", 0, 0, V_$006D72A8[0];
-V_$006CC038 .net "tx2DataIn", 7, 0, V_$006D1678[0], V_$006D1678[1], V_$006D1678[2], V_$006D1678[3], V_$006D1678[4], V_$006D1678[5], V_$006D1678[6], V_$006D1678[7];
-V_$006CBAB0 .net "tx2DataWEn", 0, 0, V_$006D17B8[0];
-V_$006CC2F8 .net "tx3DataIn", 7, 0, V_$006D71D0[0], V_$006D71D0[1], V_$006D71D0[2], V_$006D71D0[3], V_$006D71D0[4], V_$006D71D0[5], V_$006D71D0[6], V_$006D71D0[7];
-V_$006CCE78 .net "tx3DataWEn", 0, 0, V_$006DB4B8[0];
-V_$006CCF00 .net "tx4DataIn", 7, 0, V_$006DD220[0], V_$006DD220[1], V_$006DD220[2], V_$006DD220[3], V_$006DD220[4], V_$006DD220[5], V_$006DD220[6], V_$006DD220[7];
-V_$006CC720 .net "tx4DataWEn", 0, 0, V_$006DBDB0[0];
-V_$006CC7A8 .var "txDataFull", 0, 0;
-V_$006CC800 .net "txDataFullClr", 0, 0, V_$006CAC78[0];
-V_$006CC858 .var "txDataOut", 7, 0;
-S_006C9128 .scope module, "u_readWriteSPIWireData" "readWriteSPIWireData", S_006C1500;
- .timescale -9;
-V_$006C9298 .var "CurrState_rwSPISt", 1, 0;
-V_$006C92D0 .var "NextState_rwSPISt", 1, 0;
-V_$006C9BE0 .var "bitCnt", 3, 0;
-V_$006C9C18 .net "clk", 0, 0, V_$006E3508[0];
-V_$006C9CC8 .net "clkDelay", 7, 0, V_$006DB188[0], V_$006DB188[1], V_$006DB188[2], V_$006DB188[3], V_$006DB188[4], V_$006DB188[5], V_$006DB188[6], V_$006DB188[7];
-V_$006C9D00 .var "clkDelayCnt", 7, 0;
-V_$006C9FA0 .var "next_bitCnt", 3, 0;
-V_$006C9440 .var "next_clkDelayCnt", 7, 0;
-V_$006C9660 .var "next_rxDataOut", 7, 0;
-V_$006C9938 .var "next_rxDataRdySet", 0, 0;
-V_$006C99C0 .var "next_rxDataShiftReg", 7, 0;
-V_$006CA118 .var "next_spiClkOut", 0, 0;
-V_$006CA198 .var "next_spiDataOut", 0, 0;
-V_$006C99F8 .var "next_txDataEmpty", 0, 0;
-V_$006CA268 .var "next_txDataFullClr", 0, 0;
-V_$006CA2F0 .var "next_txDataShiftReg", 7, 0;
-V_$006CAEC0 .net "rst", 0, 0, V_$006DCA00[0];
-V_$006C90B8 .var "rxDataOut", 7, 0;
-V_$006CA688 .var "rxDataRdySet", 0, 0;
-V_$006CA718 .var "rxDataShiftReg", 7, 0;
-V_$006CAA28 .var "spiClkOut", 0, 0;
-V_$006CAA80 .net "spiDataIn", 0, 0, V_$00644A08[0];
-V_$006CAAD8 .var "spiDataOut", 0, 0;
-V_$006CAB30 .var "txDataEmpty", 0, 0;
-V_$006CAB90 .net "txDataFull", 0, 0, V_$006CC7A8[0];
-V_$006CAC78 .var "txDataFullClr", 0, 0;
-V_$006CAD08 .net "txDataIn", 7, 0, V_$006CC858[0], V_$006CC858[1], V_$006CC858[2], V_$006CC858[3], V_$006CC858[4], V_$006CC858[5], V_$006CC858[6], V_$006CC858[7];
-V_$006CB278 .var "txDataShiftReg", 7, 0;
-E_006C8530/0 .event edge, V_$006C9298[0], V_$006C9298[1], V_$006C90B8[0], V_$006C90B8[1];
-E_006C8530/1 .event edge, V_$006C90B8[2], V_$006C90B8[3], V_$006C90B8[4], V_$006C90B8[5];
-E_006C8530/2 .event edge, V_$006C90B8[6], V_$006C90B8[7], V_$006CAAD8[0], V_$006CAA28[0];
-E_006C8530/3 .event edge, V_$006CAC78[0], V_$006CAB30[0], V_$006CA688[0], V_$00644A08[0];
-E_006C8530/4 .event edge, V_$006CA718[0], V_$006CA718[1], V_$006CA718[2], V_$006CA718[3];
-E_006C8530/5 .event edge, V_$006CA718[4], V_$006CA718[5], V_$006CA718[6], V_$006CA718[7];
-E_006C8530/6 .event edge, V_$006C9BE0[0], V_$006C9BE0[1], V_$006C9BE0[2], V_$006C9BE0[3];
-E_006C8530/7 .event edge, V_$006CB278[0], V_$006CB278[1], V_$006CB278[2], V_$006CB278[3];
-E_006C8530/8 .event edge, V_$006CB278[4], V_$006CB278[5], V_$006CB278[6], V_$006CB278[7];
-E_006C8530/9 .event edge, V_$006DB188[0], V_$006DB188[1], V_$006DB188[2], V_$006DB188[3];
-E_006C8530/10 .event edge, V_$006DB188[4], V_$006DB188[5], V_$006DB188[6], V_$006DB188[7];
-E_006C8530/11 .event edge, V_$006C9D00[0], V_$006C9D00[1], V_$006C9D00[2], V_$006C9D00[3];
-E_006C8530/12 .event edge, V_$006C9D00[4], V_$006C9D00[5], V_$006C9D00[6], V_$006C9D00[7];
-E_006C8530/13 .event edge, V_$006CC858[0], V_$006CC858[1], V_$006CC858[2], V_$006CC858[3];
-E_006C8530/14 .event edge, V_$006CC858[4], V_$006CC858[5], V_$006CC858[6], V_$006CC858[7];
-E_006C8530/15 .event edge, V_$006CC7A8[0];
-E_006C8530 .event/or E_006C8530/0, E_006C8530/1, E_006C8530/2, E_006C8530/3, E_006C8530/4, E_006C8530/5, E_006C8530/6, E_006C8530/7, E_006C8530/8, E_006C8530/9, E_006C8530/10, E_006C8530/11, E_006C8530/12, E_006C8530/13, E_006C8530/14, E_006C8530/15;
-S_006C4F78 .scope module, "u_txFifo" "TxFifo", S_006C1500;
- .timescale -9;
-V_$006C86B0 .net "busAddress", 2, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2];
-V_$006C5188 .net "busClk", 0, 0, V_$006DF4B8[0];
-V_$006C5150 .net "busDataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006C5118 .net "busDataOut", 7, 0, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>;
-V_$006C8968 .net "busFifoSelect", 0, 0, V_$006DEA20[0];
-V_$006C89E0 .net "busStrobe_i", 0, 0, V_$006607B0[0];
-V_$006C59A8 .net "busWriteEn", 0, 0, V_$006A5C98[0];
-V_$006C5A40 .net "fifoDataOut", 7, 0, V_$006C7CF0[0], V_$006C7CF0[1], V_$006C7CF0[2], V_$006C7CF0[3], V_$006C7CF0[4], V_$006C7CF0[5], V_$006C7CF0[6], V_$006C7CF0[7];
-V_$006C8B48 .net "fifoEmpty", 0, 0, V_$006C7FF8[0];
-V_$006C8BA0 .net "fifoFull", 0, 0, V_$006C8098[0];
-V_$006C8BF8 .net "fifoREn", 0, 0, V_$006D7488[0];
-V_$006C8C68 .net "fifoWEn", 0, 0, V_$006C54B0[0];
-V_$006C8CD8 .net "forceEmptySyncToBusClk", 0, 0, V_$006C5548[0];
-V_$006C8C30 .net "forceEmptySyncToSpiClk", 0, 0, V_$006C55B8[0];
-V_$006C8D10 .net "numElementsInFifo", 15, 0, V_$006C82B8[0], V_$006C82B8[1], V_$006C82B8[2], V_$006C82B8[3], V_$006C82B8[4], V_$006C82B8[5], V_$006C82B8[6], V_$006C82B8[7], V_$006C82B8[8], V_$006C82B8[9], V_$006C82B8[10], V_$006C82B8[11], V_$006C82B8[12], V_$006C82B8[13], V_$006C82B8[14], V_$006C82B8[15];
-V_$006C9048 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0];
-V_$006C9080 .net "rstSyncToSpiClk", 0, 0, V_$006DCA00[0];
-V_$006C90F0 .net "spiSysClk", 0, 0, V_$006E3508[0];
-S_006C5A78 .scope module, "u_fifo" "fifoRTL", S_006C4F78;
- .timescale -9;
-V_$006C52C8 .var "bufferCnt", 9, 0;
-V_$006C5290 .var "bufferInIndex", 9, 0;
-V_$006C5258 .var "bufferInIndexSyncToRdClk", 9, 0;
-V_$006C7270 .var "bufferInIndexToMem", 8, 0;
-V_$006C73C8 .var "bufferOutIndex", 9, 0;
-V_$006C7F50 .var "bufferOutIndexSyncToWrClk", 9, 0;
-V_$006C77D8 .var "bufferOutIndexToMem", 8, 0;
-V_$006C7978 .net "dataFromMem", 7, 0, V_$006C53E0[0], V_$006C53E0[1], V_$006C53E0[2], V_$006C53E0[3], V_$006C53E0[4], V_$006C53E0[5], V_$006C53E0[6], V_$006C53E0[7];
-V_$006C7AD8 .net "dataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006C7CF0 .var "dataOut", 7, 0;
-V_$006C7FF8 .var "fifoEmpty", 0, 0;
-V_$006C8098 .var "fifoFull", 0, 0;
-V_$006C8118 .net "fifoREn", 0, 0, V_$006D7488[0];
-V_$006C8030 .var "fifoREnDelayed", 0, 0;
-V_$006C81A0 .net "fifoWEn", 0, 0, V_$006C54B0[0];
-V_$006C81D8 .net "forceEmptySyncToRdClk", 0, 0, V_$006C55B8[0];
-V_$006C8210 .net "forceEmptySyncToWrClk", 0, 0, V_$006C5548[0];
-V_$006C82B8 .var "numElementsInFifo", 15, 0;
-V_$006C8550 .net "rdClk", 0, 0, V_$006E3508[0];
-V_$006C85E0 .net "rstSyncToRdClk", 0, 0, V_$006DCA00[0];
-V_$006C8618 .net "rstSyncToWrClk", 0, 0, V_$006DC940[0];
-V_$006C5628 .net "wrClk", 0, 0, V_$006DF4B8[0];
-E_005F17F0/0 .event edge, V_$006C73C8[0], V_$006C73C8[1], V_$006C73C8[2], V_$006C73C8[3];
-E_005F17F0/1 .event edge, V_$006C73C8[4], V_$006C73C8[5], V_$006C73C8[6], V_$006C73C8[7];
-E_005F17F0/2 .event edge, V_$006C73C8[8], V_$006C73C8[9], V_$006C5290[0], V_$006C5290[1];
-E_005F17F0/3 .event edge, V_$006C5290[2], V_$006C5290[3], V_$006C5290[4], V_$006C5290[5];
-E_005F17F0/4 .event edge, V_$006C5290[6], V_$006C5290[7], V_$006C5290[8], V_$006C5290[9];
-E_005F17F0 .event/or E_005F17F0/0, E_005F17F0/1, E_005F17F0/2, E_005F17F0/3, E_005F17F0/4;
-E_003DDD60/0 .event edge, V_$006C73C8[0], V_$006C73C8[1], V_$006C73C8[2], V_$006C73C8[3];
-E_003DDD60/1 .event edge, V_$006C73C8[4], V_$006C73C8[5], V_$006C73C8[6], V_$006C73C8[7];
-E_003DDD60/2 .event edge, V_$006C73C8[8], V_$006C73C8[9], V_$006C5258[0], V_$006C5258[1];
-E_003DDD60/3 .event edge, V_$006C5258[2], V_$006C5258[3], V_$006C5258[4], V_$006C5258[5];
-E_003DDD60/4 .event edge, V_$006C5258[6], V_$006C5258[7], V_$006C5258[8], V_$006C5258[9];
-E_003DDD60 .event/or E_003DDD60/0, E_003DDD60/1, E_003DDD60/2, E_003DDD60/3, E_003DDD60/4;
-S_006C5C68 .scope module, "u_dpMem_dc" "dpMem_dc", S_006C5A78;
- .timescale -9;
-V_$006C5B38 .net "addrIn", 8, 0, V_$006C7270[0], V_$006C7270[1], V_$006C7270[2], V_$006C7270[3], V_$006C7270[4], V_$006C7270[5], V_$006C7270[6], V_$006C7270[7], V_$006C7270[8];
-V_$006C6048 .net "addrOut", 8, 0, V_$006C77D8[0], V_$006C77D8[1], V_$006C77D8[2], V_$006C77D8[3], V_$006C77D8[4], V_$006C77D8[5], V_$006C77D8[6], V_$006C77D8[7], V_$006C77D8[8];
-V_$006C6340 .net "dataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006C53E0 .var "dataOut", 7, 0;
-V_$006C53A8 .net "rdClk", 0, 0, V_$006E3508[0];
-V_$006C5370 .net "readEn", 0, 0, V_$006D7488[0];
-V_$006C5338 .net "wrClk", 0, 0, V_$006DF4B8[0];
-V_$006C5300 .net "writeEn", 0, 0, V_$006C54B0[0];
-M_$006C68E0 .mem "buffer", 7,0, 0,511;
-S_006C5098 .scope module, "u_TxfifoBI" "TxfifoBI", S_006C4F78;
- .timescale -9;
-V_$006C5060 .net "address", 2, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2];
-V_$006C51C0 .net "busClk", 0, 0, V_$006DF4B8[0];
-V_$006C51F8 .net "busDataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006C5418 .net "busDataOut", 7, 0, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>, C<0>;
-V_$006C5478 .net "fifoSelect", 0, 0, V_$006DEA20[0];
-V_$006C54B0 .var "fifoWEn", 0, 0;
-V_$006C54E8 .var "forceEmpty", 0, 0;
-V_$006C5548 .var "forceEmptyShift", 5, 0;
-V_$006C5580 .net "forceEmptySyncToBusClk", 0, 0, V_$006C5548[0];
-V_$006C55B8 .var "forceEmptySyncToSpiClk", 0, 0;
-V_$006C55F0 .var "forceEmptySyncToSpiClkFirst", 0, 0;
-V_$006C5660 .net "numElementsInFifo", 15, 0, V_$006C82B8[0], V_$006C82B8[1], V_$006C82B8[2], V_$006C82B8[3], V_$006C82B8[4], V_$006C82B8[5], V_$006C82B8[6], V_$006C82B8[7], V_$006C82B8[8], V_$006C82B8[9], V_$006C82B8[10], V_$006C82B8[11], V_$006C82B8[12], V_$006C82B8[13], V_$006C82B8[14], V_$006C82B8[15];
-V_$006C58F0 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0];
-V_$006C5928 .net "spiSysClk", 0, 0, V_$006E3508[0];
-V_$006C4F40 .net "strobe_i", 0, 0, V_$006607B0[0];
-V_$006C5A08 .net "writeEn", 0, 0, V_$006A5C98[0];
-E_006C45B0/0 .event edge, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3];
-E_006C45B0/1 .event edge, V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-E_006C45B0/2 .event edge, V_$006DEA20[0], V_$006607B0[0], V_$006A5C98[0], V_$0068AE60[0];
-E_006C45B0/3 .event edge, V_$0068AE60[1], V_$0068AE60[2];
-E_006C45B0 .event/or E_006C45B0/0, E_006C45B0/1, E_006C45B0/2, E_006C45B0/3;
-S_006C1570 .scope module, "u_rxFifo" "RxFifo", S_006C1500;
- .timescale -9;
-V_$006C4760 .net "busAddress", 2, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2];
-V_$006C4798 .net "busClk", 0, 0, V_$006DF4B8[0];
-V_$006C4660 .net "busDataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006C4840 .net "busDataOut", 7, 0, V_$006A5290[0], V_$006A5290[1], V_$006A5290[2], V_$006A5290[3], V_$006A5290[4], V_$006A5290[5], V_$006A5290[6], V_$006A5290[7];
-V_$006C48A0 .net "busFifoSelect", 0, 0, V_$006DE9B8[0];
-V_$006C48D8 .net "busStrobe_i", 0, 0, V_$006607B0[0];
-V_$006C4910 .net "busWriteEn", 0, 0, V_$006A5C98[0];
-V_$006C4970 .net "dataFromFifoToBus", 7, 0, V_$006C4090[0], V_$006C4090[1], V_$006C4090[2], V_$006C4090[3], V_$006C4090[4], V_$006C4090[5], V_$006C4090[6], V_$006C4090[7];
-V_$006C49D0 .net "fifoDataIn", 7, 0, V_$006D6958[0], V_$006D6958[1], V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5], V_$006D6958[6], V_$006D6958[7];
-V_$006C4A08 .net "fifoEmpty", 0, 0, V_$006C41F0[0];
-V_$006C4A40 .net "fifoFull", 0, 0, V_$006C4260[0];
-V_$006C4AB0 .net "fifoREn", 0, 0, V_$006A76F0[0];
-V_$006C4B20 .net "fifoWEn", 0, 0, V_$006D6B90[0];
-V_$006C4A78 .net "forceEmptySyncToBusClk", 0, 0, V_$00666B38[0];
-V_$006C4B58 .net "forceEmptySyncToSpiClk", 0, 0, V_$006A9EA0[0];
-V_$006C4BD8 .net "numElementsInFifo", 15, 0, V_$006C4398[0], V_$006C4398[1], V_$006C4398[2], V_$006C4398[3], V_$006C4398[4], V_$006C4398[5], V_$006C4398[6], V_$006C4398[7], V_$006C4398[8], V_$006C4398[9], V_$006C4398[10], V_$006C4398[11], V_$006C4398[12], V_$006C4398[13], V_$006C4398[14], V_$006C4398[15];
-V_$006C4E68 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0];
-V_$006C4ED0 .net "rstSyncToSpiClk", 0, 0, V_$006DCA00[0];
-V_$006C4F08 .net "spiSysClk", 0, 0, V_$006E3508[0];
-S_006C2110 .scope module, "u_fifo" "fifoRTL", S_006C1570;
- .timescale -9;
-V_$006C2810 .var "bufferCnt", 9, 0;
-V_$006C2B10 .var "bufferInIndex", 9, 0;
-V_$006C3170 .var "bufferInIndexSyncToRdClk", 9, 0;
-V_$006C3508 .var "bufferInIndexToMem", 8, 0;
-V_$006C3600 .var "bufferOutIndex", 9, 0;
-V_$006C3D38 .var "bufferOutIndexSyncToWrClk", 9, 0;
-V_$006C3740 .var "bufferOutIndexToMem", 8, 0;
-V_$006C3898 .net "dataFromMem", 7, 0, V_$00639738[0], V_$00639738[1], V_$00639738[2], V_$00639738[3], V_$00639738[4], V_$00639738[5], V_$00639738[6], V_$00639738[7];
-V_$006C39F8 .net "dataIn", 7, 0, V_$006D6958[0], V_$006D6958[1], V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5], V_$006D6958[6], V_$006D6958[7];
-V_$006C4090 .var "dataOut", 7, 0;
-V_$006C41F0 .var "fifoEmpty", 0, 0;
-V_$006C4260 .var "fifoFull", 0, 0;
-V_$006C4298 .net "fifoREn", 0, 0, V_$006A76F0[0];
-V_$006C4228 .var "fifoREnDelayed", 0, 0;
-V_$006C42D0 .net "fifoWEn", 0, 0, V_$006D6B90[0];
-V_$006C4308 .net "forceEmptySyncToRdClk", 0, 0, V_$00666B38[0];
-V_$006C4360 .net "forceEmptySyncToWrClk", 0, 0, V_$006A9EA0[0];
-V_$006C4398 .var "numElementsInFifo", 15, 0;
-V_$006C45D0 .net "rdClk", 0, 0, V_$006DF4B8[0];
-V_$006C4698 .net "rstSyncToRdClk", 0, 0, V_$006DC940[0];
-V_$006C46F0 .net "rstSyncToWrClk", 0, 0, V_$006DCA00[0];
-V_$006C4728 .net "wrClk", 0, 0, V_$006E3508[0];
-E_005EEF18/0 .event edge, V_$006C3600[0], V_$006C3600[1], V_$006C3600[2], V_$006C3600[3];
-E_005EEF18/1 .event edge, V_$006C3600[4], V_$006C3600[5], V_$006C3600[6], V_$006C3600[7];
-E_005EEF18/2 .event edge, V_$006C3600[8], V_$006C3600[9], V_$006C2B10[0], V_$006C2B10[1];
-E_005EEF18/3 .event edge, V_$006C2B10[2], V_$006C2B10[3], V_$006C2B10[4], V_$006C2B10[5];
-E_005EEF18/4 .event edge, V_$006C2B10[6], V_$006C2B10[7], V_$006C2B10[8], V_$006C2B10[9];
-E_005EEF18 .event/or E_005EEF18/0, E_005EEF18/1, E_005EEF18/2, E_005EEF18/3, E_005EEF18/4;
-E_005EE048/0 .event edge, V_$006C3600[0], V_$006C3600[1], V_$006C3600[2], V_$006C3600[3];
-E_005EE048/1 .event edge, V_$006C3600[4], V_$006C3600[5], V_$006C3600[6], V_$006C3600[7];
-E_005EE048/2 .event edge, V_$006C3600[8], V_$006C3600[9], V_$006C3170[0], V_$006C3170[1];
-E_005EE048/3 .event edge, V_$006C3170[2], V_$006C3170[3], V_$006C3170[4], V_$006C3170[5];
-E_005EE048/4 .event edge, V_$006C3170[6], V_$006C3170[7], V_$006C3170[8], V_$006C3170[9];
-E_005EE048 .event/or E_005EE048/0, E_005EE048/1, E_005EE048/2, E_005EE048/3, E_005EE048/4;
-S_006C2228 .scope module, "u_dpMem_dc" "dpMem_dc", S_006C2110;
- .timescale -9;
-V_$006AC480 .net "addrIn", 8, 0, V_$006C3508[0], V_$006C3508[1], V_$006C3508[2], V_$006C3508[3], V_$006C3508[4], V_$006C3508[5], V_$006C3508[6], V_$006C3508[7], V_$006C3508[8];
-V_$006AC4E0 .net "addrOut", 8, 0, V_$006C3740[0], V_$006C3740[1], V_$006C3740[2], V_$006C3740[3], V_$006C3740[4], V_$006C3740[5], V_$006C3740[6], V_$006C3740[7], V_$006C3740[8];
-V_$006AD2C8 .net "dataIn", 7, 0, V_$006D6958[0], V_$006D6958[1], V_$006D6958[2], V_$006D6958[3], V_$006D6958[4], V_$006D6958[5], V_$006D6958[6], V_$006D6958[7];
-V_$00639738 .var "dataOut", 7, 0;
-V_$00615800 .net "rdClk", 0, 0, V_$006DF4B8[0];
-V_$005E3868 .net "readEn", 0, 0, V_$006A76F0[0];
-V_$006C2778 .net "wrClk", 0, 0, V_$006E3508[0];
-V_$006C27D8 .net "writeEn", 0, 0, V_$006D6B90[0];
-M_$005D1E00 .mem "buffer", 7,0, 0,511;
-S_006C1658 .scope module, "u_RxfifoBI" "RxfifoBI", S_006C1570;
- .timescale -9;
-V_$006A4EE8 .net "address", 2, 0, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2];
-V_$006A6E08 .net "busClk", 0, 0, V_$006DF4B8[0];
-V_$0065A890 .net "busDataIn", 7, 0, V_$0069AA18[0], V_$0069AA18[1], V_$0069AA18[2], V_$0069AA18[3], V_$0069AA18[4], V_$0069AA18[5], V_$0069AA18[6], V_$0069AA18[7];
-V_$006A5290 .var "busDataOut", 7, 0;
-V_$00660078 .net "fifoDataIn", 7, 0, V_$006C4090[0], V_$006C4090[1], V_$006C4090[2], V_$006C4090[3], V_$006C4090[4], V_$006C4090[5], V_$006C4090[6], V_$006C4090[7];
-V_$006A76F0 .var "fifoREn", 0, 0;
-V_$006A7BA8 .net "fifoSelect", 0, 0, V_$006DE9B8[0];
-V_$006A7DD8 .var "forceEmpty", 0, 0;
-V_$00666B38 .var "forceEmptyShift", 5, 0;
-V_$006A8D90 .net "forceEmptySyncToBusClk", 0, 0, V_$00666B38[0];
-V_$006A9EA0 .var "forceEmptySyncToSpiClk", 0, 0;
-V_$006A8850 .var "forceEmptySyncToUsbClkFirst", 0, 0;
-V_$00666678 .net "numElementsInFifo", 15, 0, V_$006C4398[0], V_$006C4398[1], V_$006C4398[2], V_$006C4398[3], V_$006C4398[4], V_$006C4398[5], V_$006C4398[6], V_$006C4398[7], V_$006C4398[8], V_$006C4398[9], V_$006C4398[10], V_$006C4398[11], V_$006C4398[12], V_$006C4398[13], V_$006C4398[14], V_$006C4398[15];
-V_$0065D6E8 .net "rstSyncToBusClk", 0, 0, V_$006DC940[0];
-V_$006AACA0 .net "spiSysClk", 0, 0, V_$006E3508[0];
-V_$006AA8A8 .net "strobe_i", 0, 0, V_$006607B0[0];
-V_$006685B0 .net "writeEn", 0, 0, V_$006A5C98[0];
-E_003DDB00/0 .event edge, V_$006DE9B8[0], V_$006607B0[0], V_$006A5C98[0], V_$0068AE60[0];
-E_003DDB00/1 .event edge, V_$0068AE60[1], V_$0068AE60[2];
-E_003DDB00 .event/or E_003DDB00/0, E_003DDB00/1;
-E_003DDC30/0 .event edge, V_$006C4398[0], V_$006C4398[1], V_$006C4398[2], V_$006C4398[3];
-E_003DDC30/1 .event edge, V_$006C4398[4], V_$006C4398[5], V_$006C4398[6], V_$006C4398[7];
-E_003DDC30/2 .event edge, V_$006C4398[8], V_$006C4398[9], V_$006C4398[10], V_$006C4398[11];
-E_003DDC30/3 .event edge, V_$006C4398[12], V_$006C4398[13], V_$006C4398[14], V_$006C4398[15];
-E_003DDC30/4 .event edge, V_$006C4090[0], V_$006C4090[1], V_$006C4090[2], V_$006C4090[3];
-E_003DDC30/5 .event edge, V_$006C4090[4], V_$006C4090[5], V_$006C4090[6], V_$006C4090[7];
-E_003DDC30/6 .event edge, V_$0068AE60[0], V_$0068AE60[1], V_$0068AE60[2];
-E_003DDC30 .event/or E_003DDC30/0, E_003DDC30/1, E_003DDC30/2, E_003DDC30/3, E_003DDC30/4, E_003DDC30/5, E_003DDC30/6;
-E_003DE478 .event posedge, V_$006E3508[0];
-S_00624D88 .scope module, "u_wb_master_model" "wb_master_model", S_006338F0;
- .timescale -9;
-V_$00689E98 .net "ack", 0, 0, V_$006DE038[0];
-V_$0068AE60 .var "adr", 7, 0;
-V_$00698EA8 .net "clk", 0, 0, V_$006DF4B8[0];
-V_$0069A858 .var "cyc", 0, 0;
-V_$00657510 .net "din", 7, 0, V_$006DE8E8[0], V_$006DE8E8[1], V_$006DE8E8[2], V_$006DE8E8[3], V_$006DE8E8[4], V_$006DE8E8[5], V_$006DE8E8[6], V_$006DE8E8[7];
-V_$0069AA18 .var "dout", 7, 0;
-V_$0069FC50 .net "err", 0, 0, C<0>;
-V_$006A05F8 .var "q", 7, 0;
-V_$006A0F58 .net "rst", 0, 0, V_$006E0BD0[0];
-V_$006A10B0 .net "rty", 0, 0, C<0>;
-V_$006A4238 .var "sel", 0, 0;
-V_$006607B0 .var "stb", 0, 0;
-V_$006A5C98 .var "we", 0, 0;
-S_005FFF10 .scope task, "wb_cmp" "testHarness.u_wb_master_model.wb_cmp", S_00624D88;
- .timescale -9;
-V_$0067FD60 .var "a", 7, 0;
-V_$00682498 .var "d_exp", 7, 0;
-V_$00682CF8 .var/i "delay", 31, 0;
-TD_testHarness.u_wb_master_model.wb_cmp ;
- %load/v 32, V_$00682CF8[0], 32;
- %set/v V_$0067ECA0[0], 32, 32;
- %load/v 32, V_$0067FD60[0], 8;
- %set/v V_$0067E7C8[0], 32, 8;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006A05F8[0], 32, 8;
- %load/v 32, V_$00682498[0], 8;
- %load/v 40, V_$006A05F8[0], 8;
- %cmp/u 32, 40, 8;
- %inv 6, 1;
- %mov 32, 6, 1;
- %jmp/0xz T_0.0, 32;
- %vpi_call "$display", "Data compare error. Received %h, expected %h at time %t", V_$006A05F8, V_$00682498, $time;
-T_0.0 ;
- %end;
-S_003D31C0 .scope task, "wb_read" "testHarness.u_wb_master_model.wb_read", S_00624D88;
- .timescale -9;
-V_$0067E7C8 .var "a", 7, 0;
-V_$0067EE18 .var "d", 7, 0;
-V_$0067ECA0 .var/i "delay", 31, 0;
-TD_testHarness.u_wb_master_model.wb_read ;
- %load/v 32, V_$0067ECA0[0], 32;
-T_1.2 %cmp/u 0, 32, 32;
- %jmp/0xz T_1.3, 5;
- %add 32, 1, 32;
- %wait E_003DE0F8;
- %jmp T_1.2;
-T_1.3 ;
- %delay 1000;
- %load/v 32, V_$0067E7C8[0], 8;
- %set/v V_$0068AE60[0], 32, 8;
- %set/v V_$0069AA18[0], 2, 8;
- %set V_$0069A858[0], 1;
- %set V_$006607B0[0], 1;
- %set V_$006A5C98[0], 0;
- %set V_$006A4238[0], 1;
- %wait E_003DE0F8;
-T_1.4 ;
- %load 32, V_$00689E98[0];
- %inv 32, 1;
- %jmp/0xz T_1.5, 32;
- %wait E_003DE0F8;
- %jmp T_1.4;
-T_1.5 ;
- %delay 1000;
- %set V_$0069A858[0], 0;
- %set V_$006607B0[0], 2;
- %set/v V_$0068AE60[0], 2, 8;
- %set/v V_$0069AA18[0], 2, 8;
- %set V_$006A5C98[0], 2;
- %set V_$006A4238[0], 2;
- %load 32, V_$00657510[0];
- %load 33, V_$00657510[1];
- %load 34, V_$00657510[2];
- %load 35, V_$00657510[3];
- %load 36, V_$00657510[4];
- %load 37, V_$00657510[5];
- %load 38, V_$00657510[6];
- %load 39, V_$00657510[7];
- %set/v V_$0067EE18[0], 32, 8;
- %end;
-S_0062CD78 .scope task, "wb_write" "testHarness.u_wb_master_model.wb_write", S_00624D88;
- .timescale -9;
-V_$0067C5F0 .var "a", 7, 0;
-V_$0067D930 .var "d", 7, 0;
-V_$0067E2E8 .var/i "delay", 31, 0;
-E_003DE0F8 .event posedge, V_$006DF4B8[0];
-TD_testHarness.u_wb_master_model.wb_write ;
- %load/v 32, V_$0067E2E8[0], 32;
-T_2.6 %cmp/u 0, 32, 32;
- %jmp/0xz T_2.7, 5;
- %add 32, 1, 32;
- %wait E_003DE0F8;
- %jmp T_2.6;
-T_2.7 ;
- %delay 1000;
- %load/v 32, V_$0067C5F0[0], 8;
- %set/v V_$0068AE60[0], 32, 8;
- %load/v 32, V_$0067D930[0], 8;
- %set/v V_$0069AA18[0], 32, 8;
- %set V_$0069A858[0], 1;
- %set V_$006607B0[0], 1;
- %set V_$006A5C98[0], 1;
- %set V_$006A4238[0], 1;
- %wait E_003DE0F8;
-T_2.8 ;
- %load 32, V_$00689E98[0];
- %inv 32, 1;
- %jmp/0xz T_2.9, 32;
- %wait E_003DE0F8;
- %jmp T_2.8;
-T_2.9 ;
- %delay 1000;
- %set V_$0069A858[0], 0;
- %set V_$006607B0[0], 2;
- %set/v V_$0068AE60[0], 2, 8;
- %set/v V_$0069AA18[0], 2, 8;
- %set V_$006A5C98[0], 2;
- %set V_$006A4238[0], 2;
- %end;
-S_00633880 .scope module, "u_sdModel" "sdModel", S_006338F0;
- .timescale -9;
-V_$006B0438 .var "cnt", 7, 0;
-V_$006B0578 .var "respByte", 7, 0;
-V_$006B0718 .var "rxByte", 7, 0;
-V_$006B08C8 .var "smSt", 1, 0;
-V_$0066EE28 .net "spiCS_n", 0, 0, L_006E3660;
-V_$0063FB48 .net "spiClk", 0, 0, V_$006CAA28[0];
-V_$0067A3E8 .net "spiDataIn", 0, 0, V_$006CAAD8[0];
-V_$00644A08 .var "spiDataOut", 0, 0;
-S_005C89B8 .scope task, "setRespByte" "testHarness.u_sdModel.setRespByte", S_00633880;
- .timescale -9;
-V_$006B0310 .var "dataByte", 7, 0;
-TD_testHarness.u_sdModel.setRespByte ;
- %load/v 32, V_$006B0310[0], 8;
- %set/v V_$006B0578[0], 32, 8;
- %end;
-S_006399E8 .scope task, "txRxByte" "testHarness.u_sdModel.txRxByte", S_00633880;
- .timescale -9;
-V_$006AFF68 .var/i "i", 31, 0;
-V_$006B00C0 .var "rxData", 7, 0;
-V_$006B01E8 .var "txData", 7, 0;
-E_00639FE8 .event negedge, V_$006CAA28[0];
-E_00619EB0 .event posedge, V_$006CAA28[0];
-TD_testHarness.u_sdModel.txRxByte ;
- %load/v 32, V_$006B01E8[7], 1;
- %assign V_$00644A08[0], 0, 32;
- %set/v V_$006AFF68[0], 0, 32;
-T_4.10 ;
- %load/v 32, V_$006AFF68[0], 32;
- %mov 64, 1, 3;
- %mov 67, 0, 29;
- %cmp/s 32, 64, 32;
- %or 5, 4, 1;
- %jmp/0xz T_4.11, 5;
- %wait E_00619EB0;
- %load 32, V_$0067A3E8[0];
- %assign V_$006B00C0[0], 0, 32;
- %load/v 32, V_$006B00C0[0], 8;
- %ix/load 0, 1;
- %shiftl/i0 32, 8;
- %set/v V_$006B00C0[0], 32, 8;
- %wait E_00639FE8;
- %load/v 32, V_$006B01E8[6], 1;
- %assign V_$00644A08[0], 0, 32;
- %load/v 32, V_$006B01E8[0], 8;
- %ix/load 0, 1;
- %shiftl/i0 32, 8;
- %set/v V_$006B01E8[0], 32, 8;
- %load/v 32, V_$006AFF68[0], 32;
- %addi 32, 1, 32;
- %set/v V_$006AFF68[0], 32, 32;
- %jmp T_4.10;
-T_4.11 ;
- %end;
- .scope S_005FC090;
-T_5 ;
- %vpi_call "$write", "\n\n";
- %delay 1000000;
- %vpi_call "$write", "Testing register read/write\n";
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 1, 3;
- %set/v V_$0067C5F0[3], 0, 5;
- %set/v V_$0067D930[0], 0, 3;
- %set/v V_$0067D930[3], 1, 4;
- %set V_$0067D930[7], 0;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 0, 3;
- %set V_$0067C5F0[3], 1;
- %set/v V_$0067C5F0[4], 0, 4;
- %set V_$0067D930[0], 0;
- %set/v V_$0067D930[1], 1, 2;
- %set V_$0067D930[3], 0;
- %set V_$0067D930[4], 1;
- %set V_$0067D930[5], 0;
- %set V_$0067D930[6], 1;
- %set V_$0067D930[7], 0;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set V_$0067C5F0[0], 1;
- %set/v V_$0067C5F0[1], 0, 2;
- %set V_$0067C5F0[3], 1;
- %set/v V_$0067C5F0[4], 0, 4;
- %set/v V_$0067D930[0], 0, 2;
- %set V_$0067D930[2], 1;
- %set V_$0067D930[3], 0;
- %set/v V_$0067D930[4], 1, 2;
- %set/v V_$0067D930[6], 0, 2;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set V_$0067C5F0[0], 0;
- %set V_$0067C5F0[1], 1;
- %set V_$0067C5F0[2], 0;
- %set V_$0067C5F0[3], 1;
- %set/v V_$0067C5F0[4], 0, 4;
- %set V_$0067D930[0], 0;
- %set V_$0067D930[1], 1;
- %set/v V_$0067D930[2], 0, 2;
- %set V_$0067D930[4], 1;
- %set/v V_$0067D930[5], 0, 3;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$00682CF8[0], 1;
- %set V_$00682CF8[1], 0;
- %set/v V_$00682CF8[2], 0, 30;
- %set/v V_$0067FD60[0], 1, 3;
- %set/v V_$0067FD60[3], 0, 5;
- %set/v V_$00682498[0], 0, 3;
- %set/v V_$00682498[3], 1, 4;
- %set V_$00682498[7], 0;
- %fork TD_testHarness.u_wb_master_model.wb_cmp, S_005FFF10;
- %join;
- %set V_$00682CF8[0], 1;
- %set V_$00682CF8[1], 0;
- %set/v V_$00682CF8[2], 0, 30;
- %set/v V_$0067FD60[0], 0, 3;
- %set V_$0067FD60[3], 1;
- %set/v V_$0067FD60[4], 0, 4;
- %set V_$00682498[0], 0;
- %set/v V_$00682498[1], 1, 2;
- %set V_$00682498[3], 0;
- %set V_$00682498[4], 1;
- %set V_$00682498[5], 0;
- %set V_$00682498[6], 1;
- %set V_$00682498[7], 0;
- %fork TD_testHarness.u_wb_master_model.wb_cmp, S_005FFF10;
- %join;
- %set V_$00682CF8[0], 1;
- %set V_$00682CF8[1], 0;
- %set/v V_$00682CF8[2], 0, 30;
- %set V_$0067FD60[0], 1;
- %set/v V_$0067FD60[1], 0, 2;
- %set V_$0067FD60[3], 1;
- %set/v V_$0067FD60[4], 0, 4;
- %set/v V_$00682498[0], 0, 2;
- %set V_$00682498[2], 1;
- %set V_$00682498[3], 0;
- %set/v V_$00682498[4], 1, 2;
- %set/v V_$00682498[6], 0, 2;
- %fork TD_testHarness.u_wb_master_model.wb_cmp, S_005FFF10;
- %join;
- %set V_$00682CF8[0], 1;
- %set V_$00682CF8[1], 0;
- %set/v V_$00682CF8[2], 0, 30;
- %set V_$0067FD60[0], 0;
- %set V_$0067FD60[1], 1;
- %set V_$0067FD60[2], 0;
- %set V_$0067FD60[3], 1;
- %set/v V_$0067FD60[4], 0, 4;
- %set V_$00682498[0], 0;
- %set V_$00682498[1], 1;
- %set/v V_$00682498[2], 0, 2;
- %set V_$00682498[4], 1;
- %set/v V_$00682498[5], 0, 3;
- %fork TD_testHarness.u_wb_master_model.wb_cmp, S_005FFF10;
- %join;
- %vpi_call "$write", "Testing SPI bus direct access\n";
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set V_$0067C5F0[0], 0;
- %set V_$0067C5F0[1], 1;
- %set/v V_$0067C5F0[2], 0, 6;
- %set/v V_$0067D930[0], 0, 8;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set V_$0067C5F0[0], 0;
- %set/v V_$0067C5F0[1], 1, 2;
- %set/v V_$0067C5F0[3], 0, 5;
- %set/v V_$0067D930[0], 1, 5;
- %set V_$0067D930[5], 0;
- %set V_$0067D930[6], 1;
- %set V_$0067D930[7], 0;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 1, 2;
- %set/v V_$0067C5F0[2], 0, 6;
- %set V_$0067D930[0], 1;
- %set/v V_$0067D930[1], 0, 7;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set/v V_$0067E7C8[0], 0, 2;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
-T_5.0 ;
- %load/v 32, V_$006AD848[0], 1;
- %jmp/0xz T_5.1, 32;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set/v V_$0067E7C8[0], 0, 2;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
- %jmp T_5.0;
-T_5.1 ;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set V_$0067C5F0[0], 0;
- %set/v V_$0067C5F0[1], 1, 2;
- %set/v V_$0067C5F0[3], 0, 5;
- %set V_$0067D930[0], 0;
- %set V_$0067D930[1], 1;
- %set V_$0067D930[2], 0;
- %set V_$0067D930[3], 1;
- %set V_$0067D930[4], 0;
- %set V_$0067D930[5], 1;
- %set V_$0067D930[6], 0;
- %set V_$0067D930[7], 1;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 1, 2;
- %set/v V_$0067C5F0[2], 0, 6;
- %set V_$0067D930[0], 1;
- %set/v V_$0067D930[1], 0, 7;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set/v V_$0067E7C8[0], 0, 2;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
-T_5.2 ;
- %load/v 32, V_$006AD848[0], 1;
- %jmp/0xz T_5.3, 32;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set/v V_$0067E7C8[0], 0, 2;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
- %jmp T_5.2;
-T_5.3 ;
- %vpi_call "$write", "Testing SD init\n";
- %set V_$006B0310[0], 1;
- %set/v V_$006B0310[1], 0, 7;
- %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set V_$0067C5F0[0], 0;
- %set V_$0067C5F0[1], 1;
- %set/v V_$0067C5F0[2], 0, 6;
- %set V_$0067D930[0], 1;
- %set/v V_$0067D930[1], 0, 7;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 1, 2;
- %set/v V_$0067C5F0[2], 0, 6;
- %set V_$0067D930[0], 1;
- %set/v V_$0067D930[1], 0, 7;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %delay 60000000;
- %set/v V_$006B0310[0], 0, 8;
- %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8;
- %join;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set/v V_$0067E7C8[0], 0, 2;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
-T_5.4 ;
- %load/v 32, V_$006AD848[0], 1;
- %jmp/0xz T_5.5, 32;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set/v V_$0067E7C8[0], 0, 2;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
- %jmp T_5.4;
-T_5.5 ;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set V_$0067E7C8[0], 1;
- %set V_$0067E7C8[1], 0;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
- %load/v 32, V_$006AD848[0], 2;
- %cmpi/u 32, 0, 2;
- %jmp/0xz T_5.6, 4;
- %vpi_call "$write", "SD init test passed\n";
- %jmp T_5.7;
-T_5.6 ;
- %load/v 32, V_$006AD848[0], 2;
- %vpi_call "$write", "---- ERROR: SD init test failed. Error code = 0x%01x\n", T<32,2,u>;
-T_5.7 ;
- %vpi_call "$write", "Testing block write\n";
- %set/v V_$006AFD38[0], 0, 8;
- %set/v V_$006AFE40[0], 0, 32;
-T_5.8 ;
- %load/v 32, V_$006AFE40[0], 32;
- %mov 64, 1, 9;
- %mov 73, 0, 23;
- %cmp/s 32, 64, 32;
- %or 5, 4, 1;
- %jmp/0xz T_5.9, 5;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 0, 5;
- %set V_$0067C5F0[5], 1;
- %set/v V_$0067C5F0[6], 0, 2;
- %load/v 32, V_$006AFD38[0], 8;
- %set/v V_$0067D930[0], 32, 8;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %load/v 32, V_$006AFD38[0], 8;
- %addi 32, 1, 8;
- %set/v V_$006AFD38[0], 32, 8;
- %load/v 32, V_$006AFE40[0], 32;
- %addi 32, 1, 32;
- %set/v V_$006AFE40[0], 32, 32;
- %jmp T_5.8;
-T_5.9 ;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set V_$0067C5F0[0], 0;
- %set V_$0067C5F0[1], 1;
- %set/v V_$0067C5F0[2], 0, 6;
- %set/v V_$0067D930[0], 1, 2;
- %set/v V_$0067D930[2], 0, 6;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 1, 2;
- %set/v V_$0067C5F0[2], 0, 6;
- %set V_$0067D930[0], 1;
- %set/v V_$0067D930[1], 0, 7;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %delay 100000000;
- %set V_$006B0310[0], 1;
- %set V_$006B0310[1], 0;
- %set V_$006B0310[2], 1;
- %set/v V_$006B0310[3], 0, 5;
- %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8;
- %join;
- %delay 400000000;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set V_$0067E7C8[0], 1;
- %set V_$0067E7C8[1], 0;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
- %load/v 32, V_$006AD848[4], 2;
- %cmpi/u 32, 0, 2;
- %jmp/0xz T_5.10, 4;
- %vpi_call "$write", "SD block write passed\n";
- %jmp T_5.11;
-T_5.10 ;
- %load/v 32, V_$006AD848[4], 2;
- %vpi_call "$write", "---- ERROR: SD block write failed. Error code = 0x%01x\n", T<32,2,u>;
-T_5.11 ;
- %vpi_call "$write", "Testing block read\n";
- %set/v V_$006B0310[0], 0, 8;
- %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set V_$0067C5F0[0], 0;
- %set V_$0067C5F0[1], 1;
- %set/v V_$0067C5F0[2], 0, 6;
- %set V_$0067D930[0], 0;
- %set V_$0067D930[1], 1;
- %set/v V_$0067D930[2], 0, 6;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 1, 2;
- %set/v V_$0067C5F0[2], 0, 6;
- %set V_$0067D930[0], 1;
- %set/v V_$0067D930[1], 0, 7;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %delay 100000000;
- %set V_$006B0310[0], 1;
- %set V_$006B0310[1], 0;
- %set V_$006B0310[2], 1;
- %set/v V_$006B0310[3], 0, 5;
- %fork TD_testHarness.u_sdModel.setRespByte, S_005C89B8;
- %join;
- %delay 400000000;
- %set V_$0067ECA0[0], 1;
- %set V_$0067ECA0[1], 0;
- %set/v V_$0067ECA0[2], 0, 30;
- %set V_$0067E7C8[0], 1;
- %set V_$0067E7C8[1], 0;
- %set V_$0067E7C8[2], 1;
- %set/v V_$0067E7C8[3], 0, 5;
- %fork TD_testHarness.u_wb_master_model.wb_read, S_003D31C0;
- %join;
- %load/v 32, V_$0067EE18[0], 8;
- %set/v V_$006AD848[0], 32, 8;
- %load/v 32, V_$006AD848[2], 2;
- %cmpi/u 32, 0, 2;
- %jmp/0xz T_5.12, 4;
- %vpi_call "$write", "SD block read passed\n";
- %jmp T_5.13;
-T_5.12 ;
- %load/v 32, V_$006AD848[2], 2;
- %vpi_call "$write", "---- ERROR: SD block read failed. Error code = 0x%01x\n", T<32,2,u>;
-T_5.13 ;
- %set/v V_$006AFE40[0], 0, 32;
-T_5.14 ;
- %load/v 32, V_$006AFE40[0], 32;
- %mov 64, 1, 9;
- %mov 73, 0, 23;
- %cmp/s 32, 64, 32;
- %or 5, 4, 1;
- %jmp/0xz T_5.15, 5;
- %set V_$0067E2E8[0], 1;
- %set V_$0067E2E8[1], 0;
- %set/v V_$0067E2E8[2], 0, 30;
- %set/v V_$0067C5F0[0], 0, 5;
- %set V_$0067C5F0[5], 1;
- %set/v V_$0067C5F0[6], 0, 2;
- %load/v 32, V_$006AFD38[0], 8;
- %set/v V_$0067D930[0], 32, 8;
- %fork TD_testHarness.u_wb_master_model.wb_write, S_0062CD78;
- %join;
- %load/v 32, V_$006AFD38[0], 8;
- %addi 32, 1, 8;
- %set/v V_$006AFD38[0], 32, 8;
- %load/v 32, V_$006AFE40[0], 32;
- %addi 32, 1, 32;
- %set/v V_$006AFE40[0], 32, 32;
- %jmp T_5.14;
-T_5.15 ;
- %vpi_call "$write", "Finished all tests\n";
- %vpi_call "$stop";
- %end;
- .thread T_5;
- .scope S_006DD638;
-T_6 ;
- %wait E_006DDE28;
- %assign V_$006DE140[0], 0, 0;
- %assign V_$006DE9B8[0], 0, 0;
- %assign V_$006DEA20[0], 0, 0;
- %load 32, V_$006DE0A8[0];
- %load 33, V_$006DE0A8[1];
- %load 34, V_$006DE0A8[2];
- %load 35, V_$006DE0A8[3];
- %load 36, V_$006DE0A8[4];
- %load 37, V_$006DE0A8[5];
- %load 38, V_$006DE0A8[6];
- %load 39, V_$006DE0A8[7];
- %mov 40, 0, 4;
- %mov 44, 1, 4;
- %and 32, 40, 8;
- %cmpi/u 32, 0, 8;
- %jmp/1 T_6.0, 6;
- %cmpi/u 32, 16, 8;
- %jmp/1 T_6.1, 6;
- %cmpi/u 32, 32, 8;
- %jmp/1 T_6.2, 6;
- %ix/load 0, 8;
- %assign/v0 V_$006DE8E8[0], 0, 0;
- %jmp T_6.4;
-T_6.0 ;
- %assign V_$006DE140[0], 0, 1;
- %load 32, V_$006DE178[0];
- %load 33, V_$006DE178[1];
- %load 34, V_$006DE178[2];
- %load 35, V_$006DE178[3];
- %load 36, V_$006DE178[4];
- %load 37, V_$006DE178[5];
- %load 38, V_$006DE178[6];
- %load 39, V_$006DE178[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DE8E8[0], 0, 32;
- %jmp T_6.4;
-T_6.1 ;
- %assign V_$006DE9B8[0], 0, 1;
- %load 32, V_$006DE280[0];
- %load 33, V_$006DE280[1];
- %load 34, V_$006DE280[2];
- %load 35, V_$006DE280[3];
- %load 36, V_$006DE280[4];
- %load 37, V_$006DE280[5];
- %load 38, V_$006DE280[6];
- %load 39, V_$006DE280[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DE8E8[0], 0, 32;
- %jmp T_6.4;
-T_6.2 ;
- %assign V_$006DEA20[0], 0, 1;
- %load 32, V_$006DE3A0[0];
- %load 33, V_$006DE3A0[1];
- %load 34, V_$006DE3A0[2];
- %load 35, V_$006DE3A0[3];
- %load 36, V_$006DE3A0[4];
- %load 37, V_$006DE3A0[5];
- %load 38, V_$006DE3A0[6];
- %load 39, V_$006DE3A0[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DE8E8[0], 0, 32;
- %jmp T_6.4;
-T_6.4 ;
- %jmp T_6;
- .thread T_6, $push;
- .scope S_006DD638;
-T_7 ;
- %wait E_003DE0F8;
- %load 32, V_$006DE920[0];
- %assign V_$006DDE60[0], 0, 32;
- %jmp T_7;
- .thread T_7;
- .scope S_006DD638;
-T_8 ;
- %wait E_006DDDF8;
- %load 32, V_$006DE920[0];
- %assign V_$006DDEE0[0], 0, 32;
- %jmp T_8;
- .thread T_8, $push;
- .scope S_006DD638;
-T_9 ;
- %wait E_006DDDA0;
- %load 32, V_$006DEA88[0];
- %cmpi/u 32, 0, 1;
- %mov 32, 4, 1;
- %load 33, V_$006DE0A8[0];
- %load 34, V_$006DE0A8[1];
- %load 35, V_$006DE0A8[2];
- %load 36, V_$006DE0A8[3];
- %load 37, V_$006DE0A8[4];
- %load 38, V_$006DE0A8[5];
- %load 39, V_$006DE0A8[6];
- %load 40, V_$006DE0A8[7];
- %cmpi/u 33, 16, 8;
- %mov 33, 4, 1;
- %load 34, V_$006DE0A8[0];
- %load 35, V_$006DE0A8[1];
- %load 36, V_$006DE0A8[2];
- %load 37, V_$006DE0A8[3];
- %load 38, V_$006DE0A8[4];
- %load 39, V_$006DE0A8[5];
- %load 40, V_$006DE0A8[6];
- %load 41, V_$006DE0A8[7];
- %cmpi/u 34, 32, 8;
- %mov 34, 4, 1;
- %or 33, 34, 1;
- %and 32, 33, 1;
- %jmp/0xz T_9.0, 32;
- %load/v 32, V_$006DDE60[0], 1;
- %assign V_$006DE038[0], 0, 32;
- %jmp T_9.1;
-T_9.0 ;
- %load/v 32, V_$006DDEE0[0], 1;
- %assign V_$006DE038[0], 0, 32;
-T_9.1 ;
- %jmp T_9;
- .thread T_9, $push;
- .scope S_006DBE08;
-T_10 ;
- %wait E_003DE0F8;
- %load/v 32, V_$006DC940[0], 1;
- %jmp/0xz T_10.0, 32;
- %assign V_$006DDC18[0], 0, 0;
- %assign V_$006DDC18[1], 0, 0;
- %assign V_$006DD6A8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006DD380[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006DCA38[0], 0, 0;
- %jmp T_10.1;
-T_10.0 ;
- %load 32, V_$006DDD18[0];
- %load 33, V_$006DC5B0[0];
- %and 32, 33, 1;
- %load 33, V_$006DDCE0[0];
- %and 32, 33, 1;
- %load 33, V_$006DCEF8[0];
- %load 34, V_$006DCEF8[1];
- %load 35, V_$006DCEF8[2];
- %load 36, V_$006DCEF8[3];
- %load 37, V_$006DCEF8[4];
- %load 38, V_$006DCEF8[5];
- %load 39, V_$006DCEF8[6];
- %load 40, V_$006DCEF8[7];
- %cmpi/u 33, 1, 8;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %load 33, V_$006DC5E8[1];
- %and 32, 33, 1;
- %jmp/0xz T_10.2, 32;
- %assign V_$006DC6B8[0], 0, 1;
- %jmp T_10.3;
-T_10.2 ;
- %assign V_$006DC6B8[0], 0, 0;
-T_10.3 ;
- %load 32, V_$006DDD18[0];
- %load 33, V_$006DC5B0[0];
- %and 32, 33, 1;
- %load 33, V_$006DDCE0[0];
- %and 32, 33, 1;
- %load 33, V_$006DCEF8[0];
- %load 34, V_$006DCEF8[1];
- %load 35, V_$006DCEF8[2];
- %load 36, V_$006DCEF8[3];
- %load 37, V_$006DCEF8[4];
- %load 38, V_$006DCEF8[5];
- %load 39, V_$006DCEF8[6];
- %load 40, V_$006DCEF8[7];
- %cmpi/u 33, 3, 8;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %load 33, V_$006DC5E8[0];
- %and 32, 33, 1;
- %jmp/0xz T_10.4, 32;
- %assign V_$006DD6A8[0], 0, 1;
- %jmp T_10.5;
-T_10.4 ;
- %assign V_$006DD6A8[0], 0, 0;
-T_10.5 ;
- %load 32, V_$006DDD18[0];
- %load 33, V_$006DC5B0[0];
- %and 32, 33, 1;
- %load 33, V_$006DDCE0[0];
- %and 32, 33, 1;
- %jmp/0xz T_10.6, 32;
- %load 32, V_$006DCEF8[0];
- %load 33, V_$006DCEF8[1];
- %load 34, V_$006DCEF8[2];
- %load 35, V_$006DCEF8[3];
- %load 36, V_$006DCEF8[4];
- %load 37, V_$006DCEF8[5];
- %load 38, V_$006DCEF8[6];
- %load 39, V_$006DCEF8[7];
- %cmpi/u 32, 2, 8;
- %jmp/1 T_10.8, 6;
- %cmpi/u 32, 7, 8;
- %jmp/1 T_10.9, 6;
- %cmpi/u 32, 8, 8;
- %jmp/1 T_10.10, 6;
- %cmpi/u 32, 9, 8;
- %jmp/1 T_10.11, 6;
- %cmpi/u 32, 10, 8;
- %jmp/1 T_10.12, 6;
- %cmpi/u 32, 11, 8;
- %jmp/1 T_10.13, 6;
- %cmpi/u 32, 6, 8;
- %jmp/1 T_10.14, 6;
- %jmp T_10.15;
-T_10.8 ;
- %load 32, V_$006DC5E8[0];
- %load 33, V_$006DC5E8[1];
- %assign V_$006DDC18[0], 0, 32;
- %assign V_$006DDC18[1], 0, 33;
- %jmp T_10.15;
-T_10.9 ;
- %load 32, V_$006DC5E8[0];
- %load 33, V_$006DC5E8[1];
- %load 34, V_$006DC5E8[2];
- %load 35, V_$006DC5E8[3];
- %load 36, V_$006DC5E8[4];
- %load 37, V_$006DC5E8[5];
- %load 38, V_$006DC5E8[6];
- %load 39, V_$006DC5E8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DBED8[0], 0, 32;
- %jmp T_10.15;
-T_10.10 ;
- %load 32, V_$006DC5E8[0];
- %load 33, V_$006DC5E8[1];
- %load 34, V_$006DC5E8[2];
- %load 35, V_$006DC5E8[3];
- %load 36, V_$006DC5E8[4];
- %load 37, V_$006DC5E8[5];
- %load 38, V_$006DC5E8[6];
- %load 39, V_$006DC5E8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DBED8[8], 0, 32;
- %jmp T_10.15;
-T_10.11 ;
- %load 32, V_$006DC5E8[0];
- %load 33, V_$006DC5E8[1];
- %load 34, V_$006DC5E8[2];
- %load 35, V_$006DC5E8[3];
- %load 36, V_$006DC5E8[4];
- %load 37, V_$006DC5E8[5];
- %load 38, V_$006DC5E8[6];
- %load 39, V_$006DC5E8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DBED8[16], 0, 32;
- %jmp T_10.15;
-T_10.12 ;
- %load 32, V_$006DC5E8[0];
- %load 33, V_$006DC5E8[1];
- %load 34, V_$006DC5E8[2];
- %load 35, V_$006DC5E8[3];
- %load 36, V_$006DC5E8[4];
- %load 37, V_$006DC5E8[5];
- %load 38, V_$006DC5E8[6];
- %load 39, V_$006DC5E8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DBED8[24], 0, 32;
- %jmp T_10.15;
-T_10.13 ;
- %load 32, V_$006DC5E8[0];
- %load 33, V_$006DC5E8[1];
- %load 34, V_$006DC5E8[2];
- %load 35, V_$006DC5E8[3];
- %load 36, V_$006DC5E8[4];
- %load 37, V_$006DC5E8[5];
- %load 38, V_$006DC5E8[6];
- %load 39, V_$006DC5E8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DCA38[0], 0, 32;
- %jmp T_10.15;
-T_10.14 ;
- %load 32, V_$006DC5E8[0];
- %load 33, V_$006DC5E8[1];
- %load 34, V_$006DC5E8[2];
- %load 35, V_$006DC5E8[3];
- %load 36, V_$006DC5E8[4];
- %load 37, V_$006DC5E8[5];
- %load 38, V_$006DC5E8[6];
- %load 39, V_$006DC5E8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DD380[0], 0, 32;
- %jmp T_10.15;
-T_10.15 ;
-T_10.6 ;
-T_10.1 ;
- %jmp T_10;
- .thread T_10;
- .scope S_006DBE08;
-T_11 ;
- %wait E_006DBEB8;
- %load 32, V_$006DCEF8[0];
- %load 33, V_$006DCEF8[1];
- %load 34, V_$006DCEF8[2];
- %load 35, V_$006DCEF8[3];
- %load 36, V_$006DCEF8[4];
- %load 37, V_$006DCEF8[5];
- %load 38, V_$006DCEF8[6];
- %load 39, V_$006DCEF8[7];
- %cmpi/u 32, 0, 8;
- %jmp/1 T_11.0, 6;
- %cmpi/u 32, 2, 8;
- %jmp/1 T_11.1, 6;
- %cmpi/u 32, 3, 8;
- %jmp/1 T_11.2, 6;
- %cmpi/u 32, 4, 8;
- %jmp/1 T_11.3, 6;
- %cmpi/u 32, 5, 8;
- %jmp/1 T_11.4, 6;
- %cmpi/u 32, 7, 8;
- %jmp/1 T_11.5, 6;
- %cmpi/u 32, 8, 8;
- %jmp/1 T_11.6, 6;
- %cmpi/u 32, 9, 8;
- %jmp/1 T_11.7, 6;
- %cmpi/u 32, 10, 8;
- %jmp/1 T_11.8, 6;
- %cmpi/u 32, 11, 8;
- %jmp/1 T_11.9, 6;
- %cmpi/u 32, 6, 8;
- %jmp/1 T_11.10, 6;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 0;
- %jmp T_11.12;
-T_11.0 ;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 0;
- %jmp T_11.12;
-T_11.1 ;
- %load/v 32, V_$006DDC18[0], 2;
- %mov 34, 0, 6;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.2 ;
- %load/v 32, V_$006DD6A8[0], 1;
- %mov 33, 0, 7;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.3 ;
- %load/v 32, V_$006DDAA8[0], 1;
- %mov 33, 0, 7;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.4 ;
- %load/v 32, V_$006DC440[0], 2;
- %load/v 34, V_$006DC4D0[0], 2;
- %load/v 36, V_$006DCE80[0], 2;
- %mov 38, 0, 2;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.5 ;
- %load/v 32, V_$006DBED8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.6 ;
- %load/v 32, V_$006DBED8[8], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.7 ;
- %load/v 32, V_$006DBED8[16], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.8 ;
- %load/v 32, V_$006DBED8[24], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.9 ;
- %load/v 32, V_$006DCA38[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.10 ;
- %load/v 32, V_$006DD078[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DC658[0], 0, 32;
- %jmp T_11.12;
-T_11.12 ;
- %jmp T_11;
- .thread T_11, $push;
- .scope S_006DBE08;
-T_12 ;
- %wait E_003DE0F8;
- %load 32, V_$006DC620[0];
- %load/v 33, V_$006DC6B8[0], 1;
- %or 32, 33, 1;
- %jmp/0xz T_12.0, 32;
- %ix/load 0, 6;
- %assign/v0 V_$006DC710[0], 0, 1;
- %jmp T_12.1;
-T_12.0 ;
- %load/v 32, V_$006DC710[1], 5;
- %mov 37, 0, 1;
- %ix/load 0, 6;
- %assign/v0 V_$006DC710[0], 0, 32;
-T_12.1 ;
- %jmp T_12;
- .thread T_12;
- .scope S_006DBE08;
-T_13 ;
- %wait E_006DBE78;
- %load/v 32, V_$006DC710[0], 1;
- %assign V_$006DC940[0], 0, 32;
- %jmp T_13;
- .thread T_13, $push;
- .scope S_006DBE08;
-T_14 ;
- %wait E_003DE478;
- %load/v 32, V_$006DC940[0], 1;
- %assign V_$006DC978[0], 0, 32;
- %load/v 32, V_$006DC978[0], 1;
- %assign V_$006DCA00[0], 0, 32;
- %jmp T_14;
- .thread T_14;
- .scope S_006DBE08;
-T_15 ;
- %wait E_003DE0F8;
- %load/v 32, V_$006DC940[0], 1;
- %jmp/0xz T_15.0, 32;
- %ix/load 0, 6;
- %assign/v0 V_$006DD6E0[0], 0, 0;
- %jmp T_15.1;
-T_15.0 ;
- %load/v 32, V_$006DD6A8[0], 1;
- %jmp/0xz T_15.2, 32;
- %ix/load 0, 6;
- %assign/v0 V_$006DD6E0[0], 0, 1;
- %jmp T_15.3;
-T_15.2 ;
- %load/v 32, V_$006DD6E0[1], 5;
- %mov 37, 0, 1;
- %ix/load 0, 6;
- %assign/v0 V_$006DD6E0[0], 0, 32;
-T_15.3 ;
-T_15.1 ;
- %jmp T_15;
- .thread T_15;
- .scope S_006DBE08;
-T_16 ;
- %wait E_003DE478;
- %load/v 32, V_$006DD6E0[0], 1;
- %assign V_$006DDF80[0], 0, 32;
- %jmp T_16;
- .thread T_16;
- .scope S_006DBE08;
-T_17 ;
- %wait E_003DE478;
- %load/v 32, V_$006DCA00[0], 1;
- %jmp/0xz T_17.0, 32;
- %assign V_$006DDBA0[0], 0, 0;
- %assign V_$006DDBA0[1], 0, 0;
- %assign V_$006DDF80[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006DD220[0], 0, 0;
- %jmp T_17.1;
-T_17.0 ;
- %load/v 32, V_$006DD380[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DD220[0], 0, 32;
- %load/v 32, V_$006DDC18[0], 2;
- %assign V_$006DDBA0[0], 0, 32;
- %assign V_$006DDBA0[1], 0, 33;
- %load/v 32, V_$006DD380[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DD220[0], 0, 32;
-T_17.1 ;
- %jmp T_17;
- .thread T_17;
- .scope S_006DBE08;
-T_18 ;
- %wait E_003DE0F8;
- %load/v 32, V_$006DC940[0], 1;
- %jmp/0xz T_18.0, 32;
- %assign V_$006DDAA8[0], 0, 0;
- %assign V_$006DD970[0], 0, 0;
- %assign V_$006DD9E0[0], 0, 0;
- %jmp T_18.1;
-T_18.0 ;
- %load 32, V_$006DD918[0];
- %assign V_$006DD970[0], 0, 32;
- %load/v 32, V_$006DD970[0], 1;
- %assign V_$006DD9E0[0], 0, 32;
- %load/v 32, V_$006DD6A8[0], 1;
- %jmp/0xz T_18.2, 32;
- %assign V_$006DDAA8[0], 0, 1;
- %jmp T_18.3;
-T_18.2 ;
- %load/v 32, V_$006DD9E0[0], 1;
- %load/v 33, V_$006DD970[0], 1;
- %cmpi/u 33, 0, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_18.4, 32;
- %assign V_$006DDAA8[0], 0, 0;
-T_18.4 ;
-T_18.3 ;
-T_18.1 ;
- %load 32, V_$006DCBF0[0];
- %load 33, V_$006DCBF0[1];
- %load 34, V_$006DCBF0[2];
- %load 35, V_$006DCBF0[3];
- %load 36, V_$006DCBF0[4];
- %load 37, V_$006DCBF0[5];
- %load 38, V_$006DCBF0[6];
- %load 39, V_$006DCBF0[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DD078[0], 0, 32;
- %load 32, V_$006DCE08[0];
- %load 33, V_$006DCE08[1];
- %assign V_$006DCE80[0], 0, 32;
- %assign V_$006DCE80[1], 0, 33;
- %load 32, V_$006DC478[0];
- %load 33, V_$006DC478[1];
- %assign V_$006DC4D0[0], 0, 32;
- %assign V_$006DC4D0[1], 0, 33;
- %load 32, V_$006DC3C8[0];
- %load 33, V_$006DC3C8[1];
- %assign V_$006DC440[0], 0, 32;
- %assign V_$006DC440[1], 0, 33;
- %jmp T_18;
- .thread T_18;
- .scope S_006DA008;
-T_19 ;
- %wait E_006DB510;
- %load/v 32, V_$006DB530[0], 3;
- %ix/load 0, 3;
- %assign/v0 V_$006DB5C8[0], 0, 32;
- %load/v 32, V_$006DBA28[0], 2;
- %assign V_$006DB760[0], 0, 32;
- %assign V_$006DB760[1], 0, 33;
- %load/v 32, V_$006DBDB0[0], 1;
- %assign V_$006DB918[0], 0, 32;
- %load/v 32, V_$006DB678[0], 1;
- %assign V_$006DB728[0], 0, 32;
- %load/v 32, V_$006DAC70[0], 1;
- %assign V_$006DB7C0[0], 0, 32;
- %load/v 32, V_$006DBC48[0], 1;
- %assign V_$006DB890[0], 0, 32;
- %load/v 32, V_$006DBBB8[0], 1;
- %assign V_$006DB810[0], 0, 32;
- %load/v 32, V_$006DB530[0], 3;
- %cmpi/u 32, 0, 3;
- %jmp/1 T_19.0, 6;
- %cmpi/u 32, 1, 3;
- %jmp/1 T_19.1, 6;
- %cmpi/u 32, 2, 3;
- %jmp/1 T_19.2, 6;
- %cmpi/u 32, 3, 3;
- %jmp/1 T_19.3, 6;
- %cmpi/u 32, 4, 3;
- %jmp/1 T_19.4, 6;
- %cmpi/u 32, 5, 3;
- %jmp/1 T_19.5, 6;
- %cmpi/u 32, 6, 3;
- %jmp/1 T_19.6, 6;
- %cmpi/u 32, 7, 3;
- %jmp/1 T_19.7, 6;
- %jmp T_19.8;
-T_19.0 ;
- %assign V_$006DB760[0], 0, 0;
- %assign V_$006DB760[1], 0, 0;
- %assign V_$006DB918[0], 0, 0;
- %assign V_$006DB728[0], 0, 0;
- %assign V_$006DB7C0[0], 0, 0;
- %assign V_$006DB890[0], 0, 0;
- %assign V_$006DB810[0], 0, 1;
- %assign V_$006DB5C8[0], 0, 1;
- %assign V_$006DB5C8[1], 0, 0;
- %assign V_$006DB5C8[2], 0, 0;
- %jmp T_19.8;
-T_19.1 ;
- %assign V_$006DB7C0[0], 0, 0;
- %assign V_$006DB890[0], 0, 0;
- %load 32, V_$006DBC10[0];
- %load 33, V_$006DBCC8[0];
- %load 34, V_$006DBCC8[1];
- %cmpi/u 33, 1, 2;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_19.9, 32;
- %assign V_$006DB5C8[0], 0, 0;
- %assign V_$006DB5C8[1], 0, 0;
- %assign V_$006DB5C8[2], 0, 1;
- %assign V_$006DB890[0], 0, 1;
- %assign V_$006DB728[0], 0, 1;
- %jmp T_19.10;
-T_19.9 ;
- %load 32, V_$006DBC10[0];
- %load 33, V_$006DBCC8[0];
- %load 34, V_$006DBCC8[1];
- %cmpi/u 33, 3, 2;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_19.11, 32;
- %assign V_$006DB5C8[0], 0, 0;
- %assign V_$006DB5C8[1], 0, 1;
- %assign V_$006DB5C8[2], 0, 1;
- %assign V_$006DB890[0], 0, 1;
- %assign V_$006DB760[0], 0, 1;
- %assign V_$006DB760[1], 0, 0;
- %jmp T_19.12;
-T_19.11 ;
- %load 32, V_$006DBC10[0];
- %load 33, V_$006DBCC8[0];
- %load 34, V_$006DBCC8[1];
- %cmpi/u 33, 2, 2;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_19.13, 32;
- %assign V_$006DB5C8[0], 0, 0;
- %assign V_$006DB5C8[1], 0, 1;
- %assign V_$006DB5C8[2], 0, 1;
- %assign V_$006DB890[0], 0, 1;
- %assign V_$006DB760[0], 0, 0;
- %assign V_$006DB760[1], 0, 1;
- %jmp T_19.14;
-T_19.13 ;
- %load 32, V_$006DBC10[0];
- %load 33, V_$006DBCC8[0];
- %load 34, V_$006DBCC8[1];
- %cmpi/u 33, 0, 2;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_19.15, 32;
- %assign V_$006DB5C8[0], 0, 1;
- %assign V_$006DB5C8[1], 0, 1;
- %assign V_$006DB5C8[2], 0, 0;
- %assign V_$006DB890[0], 0, 1;
- %assign V_$006DB918[0], 0, 1;
- %assign V_$006DB810[0], 0, 0;
-T_19.15 ;
-T_19.14 ;
-T_19.12 ;
-T_19.10 ;
- %jmp T_19.8;
-T_19.2 ;
- %load 32, V_$006DBB18[0];
- %jmp/0xz T_19.17, 32;
- %assign V_$006DB5C8[0], 0, 1;
- %assign V_$006DB5C8[1], 0, 0;
- %assign V_$006DB5C8[2], 0, 0;
- %assign V_$006DB7C0[0], 0, 1;
- %assign V_$006DB810[0], 0, 1;
-T_19.17 ;
- %jmp T_19.8;
-T_19.3 ;
- %assign V_$006DB918[0], 0, 0;
- %assign V_$006DB5C8[0], 0, 0;
- %assign V_$006DB5C8[1], 0, 1;
- %assign V_$006DB5C8[2], 0, 0;
- %jmp T_19.8;
-T_19.4 ;
- %assign V_$006DB728[0], 0, 0;
- %assign V_$006DB5C8[0], 0, 1;
- %assign V_$006DB5C8[1], 0, 0;
- %assign V_$006DB5C8[2], 0, 1;
- %jmp T_19.8;
-T_19.5 ;
- %load 32, V_$006DB620[0];
- %jmp/0xz T_19.19, 32;
- %assign V_$006DB5C8[0], 0, 1;
- %assign V_$006DB5C8[1], 0, 0;
- %assign V_$006DB5C8[2], 0, 0;
-T_19.19 ;
- %jmp T_19.8;
-T_19.6 ;
- %assign V_$006DB760[0], 0, 0;
- %assign V_$006DB760[1], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006DB5C8[0], 0, 1;
- %jmp T_19.8;
-T_19.7 ;
- %load 32, V_$006DB9D0[0];
- %jmp/0xz T_19.21, 32;
- %assign V_$006DB5C8[0], 0, 1;
- %assign V_$006DB5C8[1], 0, 0;
- %assign V_$006DB5C8[2], 0, 0;
-T_19.21 ;
- %jmp T_19.8;
-T_19.8 ;
- %jmp T_19;
- .thread T_19, $push;
- .scope S_006DA008;
-T_20 ;
- %wait E_003DE478;
- %load 32, V_$006DB950[0];
- %jmp/0xz T_20.0, 32;
- %ix/load 0, 3;
- %assign/v0 V_$006DB530[0], 0, 0;
- %jmp T_20.1;
-T_20.0 ;
- %load/v 32, V_$006DB5C8[0], 3;
- %ix/load 0, 3;
- %assign/v0 V_$006DB530[0], 0, 32;
-T_20.1 ;
- %jmp T_20;
- .thread T_20;
- .scope S_006DA008;
-T_21 ;
- %wait E_003DE478;
- %load 32, V_$006DB950[0];
- %jmp/0xz T_21.0, 32;
- %assign V_$006DBA28[0], 0, 0;
- %assign V_$006DBA28[1], 0, 0;
- %assign V_$006DBDB0[0], 0, 0;
- %assign V_$006DB678[0], 0, 0;
- %assign V_$006DAC70[0], 0, 0;
- %assign V_$006DBC48[0], 0, 0;
- %assign V_$006DBBB8[0], 0, 1;
- %jmp T_21.1;
-T_21.0 ;
- %load/v 32, V_$006DB760[0], 2;
- %assign V_$006DBA28[0], 0, 32;
- %assign V_$006DBA28[1], 0, 33;
- %load/v 32, V_$006DB918[0], 1;
- %assign V_$006DBDB0[0], 0, 32;
- %load/v 32, V_$006DB728[0], 1;
- %assign V_$006DB678[0], 0, 32;
- %load/v 32, V_$006DB7C0[0], 1;
- %assign V_$006DAC70[0], 0, 32;
- %load/v 32, V_$006DB890[0], 1;
- %assign V_$006DBC48[0], 0, 32;
- %load/v 32, V_$006DB810[0], 1;
- %assign V_$006DBBB8[0], 0, 32;
-T_21.1 ;
- %jmp T_21;
- .thread T_21;
- .scope S_006D5E10;
-T_22 ;
- %wait E_006C8B28;
- %load/v 32, V_$006D7810[0], 4;
- %ix/load 0, 4;
- %assign/v0 V_$006D78C0[0], 0, 32;
- %load/v 32, V_$006DB188[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DA4D0[0], 0, 32;
- %load/v 32, V_$006D7E68[0], 1;
- %assign V_$006D8560[0], 0, 32;
- %load/v 32, V_$006DADF8[0], 1;
- %assign V_$006DA450[0], 0, 32;
- %load/v 32, V_$006D8260[0], 2;
- %assign V_$006D9D58[0], 0, 32;
- %assign V_$006D9D58[1], 0, 33;
- %load/v 32, V_$006D71D0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DA638[0], 0, 32;
- %load/v 32, V_$006DB4B8[0], 1;
- %assign V_$006DA918[0], 0, 32;
- %load/v 32, V_$006D7B08[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D8900[0], 0, 32;
- %load/v 32, V_$006D7C70[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D8B78[0], 0, 32;
- %load/v 32, V_$006D7DD0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D90D8[0], 0, 32;
- %load/v 32, V_$006D80C8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D93B8[0], 0, 32;
- %load/v 32, V_$006D8228[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D9F90[0], 0, 32;
- %load/v 32, V_$006D7F80[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D85E0[0], 0, 32;
- %load/v 32, V_$006DAD18[0], 1;
- %assign V_$006DA3D0[0], 0, 32;
- %load/v 32, V_$006D8E20[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DA0A8[0], 0, 32;
- %load/v 32, V_$006D83C0[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D9750[0], 0, 32;
- %load/v 32, V_$006D83F8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D9AB8[0], 0, 32;
- %load/v 32, V_$006DACA8[0], 1;
- %assign V_$006DA348[0], 0, 32;
- %load/v 32, V_$006D7810[0], 4;
- %cmpi/u 32, 0, 4;
- %jmp/1 T_22.0, 6;
- %cmpi/u 32, 1, 4;
- %jmp/1 T_22.1, 6;
- %cmpi/u 32, 2, 4;
- %jmp/1 T_22.2, 6;
- %cmpi/u 32, 3, 4;
- %jmp/1 T_22.3, 6;
- %cmpi/u 32, 13, 4;
- %jmp/1 T_22.4, 6;
- %cmpi/u 32, 4, 4;
- %jmp/1 T_22.5, 6;
- %cmpi/u 32, 5, 4;
- %jmp/1 T_22.6, 6;
- %cmpi/u 32, 6, 4;
- %jmp/1 T_22.7, 6;
- %cmpi/u 32, 7, 4;
- %jmp/1 T_22.8, 6;
- %cmpi/u 32, 8, 4;
- %jmp/1 T_22.9, 6;
- %cmpi/u 32, 9, 4;
- %jmp/1 T_22.10, 6;
- %cmpi/u 32, 10, 4;
- %jmp/1 T_22.11, 6;
- %cmpi/u 32, 11, 4;
- %jmp/1 T_22.12, 6;
- %cmpi/u 32, 12, 4;
- %jmp/1 T_22.13, 6;
- %jmp T_22.14;
-T_22.0 ;
- %load 32, V_$006DAE30[0];
- %load 33, V_$006DAE30[1];
- %load 34, V_$006DAE30[2];
- %load 35, V_$006DAE30[3];
- %load 36, V_$006DAE30[4];
- %load 37, V_$006DAE30[5];
- %load 38, V_$006DAE30[6];
- %load 39, V_$006DAE30[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DA4D0[0], 0, 32;
- %assign V_$006D8560[0], 0, 0;
- %assign V_$006DA450[0], 0, 1;
- %assign V_$006D9D58[0], 0, 0;
- %assign V_$006D9D58[1], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006DA638[0], 0, 0;
- %assign V_$006DA918[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D8900[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D8B78[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D90D8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D93B8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D9F90[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D85E0[0], 0, 0;
- %assign V_$006DA3D0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006DA0A8[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D9750[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D9AB8[0], 0, 0;
- %assign V_$006DA348[0], 0, 0;
- %assign V_$006D78C0[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D78C0[1], 0, 0;
- %jmp T_22.14;
-T_22.1 ;
- %assign V_$006D8560[0], 0, 1;
- %load 32, V_$006DAE30[0];
- %load 33, V_$006DAE30[1];
- %load 34, V_$006DAE30[2];
- %load 35, V_$006DAE30[3];
- %load 36, V_$006DAE30[4];
- %load 37, V_$006DAE30[5];
- %load 38, V_$006DAE30[6];
- %load 39, V_$006DAE30[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DA4D0[0], 0, 32;
- %load 32, V_$006D7F00[0];
- %jmp/0xz T_22.15, 32;
- %assign V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[1], 0, 1;
- %assign V_$006D78C0[2], 0, 0;
- %assign V_$006D78C0[3], 0, 0;
- %assign V_$006D8560[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006DA0A8[0], 0, 0;
- %assign V_$006DA4D0[0], 0, 1;
- %assign V_$006DA4D0[1], 0, 1;
- %assign V_$006DA4D0[2], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006DA4D0[3], 0, 1;
- %assign V_$006DA4D0[6], 0, 0;
- %assign V_$006DA4D0[7], 0, 0;
- %assign V_$006D9D58[0], 0, 0;
- %assign V_$006D9D58[1], 0, 0;
-T_22.15 ;
- %jmp T_22.14;
-T_22.2 ;
- %load 32, V_$006DB358[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_22.17, 4;
- %assign V_$006D78C0[0], 0, 1;
- %assign V_$006D78C0[1], 0, 1;
- %assign V_$006D78C0[2], 0, 0;
- %assign V_$006D78C0[3], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006DA638[0], 0, 1;
- %assign V_$006DA918[0], 0, 1;
- %load/v 32, V_$006D8E20[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DA0A8[0], 0, 32;
-T_22.17 ;
- %jmp T_22.14;
-T_22.3 ;
- %assign V_$006DA918[0], 0, 0;
- %load/v 32, V_$006D8E20[0], 8;
- %cmpi/u 32, 160, 8;
- %jmp/0xz T_22.19, 4;
- %assign V_$006D78C0[0], 0, 1;
- %assign V_$006D78C0[1], 0, 0;
- %assign V_$006D78C0[2], 0, 1;
- %assign V_$006D78C0[3], 0, 1;
- %jmp T_22.20;
-T_22.19 ;
- %assign V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[1], 0, 1;
- %assign V_$006D78C0[2], 0, 0;
- %assign V_$006D78C0[3], 0, 0;
-T_22.20 ;
- %jmp T_22.14;
-T_22.4 ;
- %load 32, V_$006DB2E8[0];
- %jmp/0xz T_22.21, 32;
- %assign V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[1], 0, 0;
- %assign V_$006D78C0[2], 0, 1;
- %assign V_$006D78C0[3], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006DA0A8[0], 0, 0;
-T_22.21 ;
- %jmp T_22.14;
-T_22.5 ;
- %ix/load 0, 6;
- %assign/v0 V_$006D8900[0], 0, 0;
- %assign V_$006D8900[6], 0, 1;
- %assign V_$006D8900[7], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D8B78[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D90D8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D93B8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D9F90[0], 0, 0;
- %assign V_$006D85E0[0], 0, 1;
- %assign V_$006D85E0[1], 0, 0;
- %assign V_$006D85E0[2], 0, 1;
- %assign V_$006D85E0[3], 0, 0;
- %assign V_$006D85E0[4], 0, 1;
- %assign V_$006D85E0[5], 0, 0;
- %assign V_$006D85E0[6], 0, 0;
- %assign V_$006D85E0[7], 0, 1;
- %assign V_$006DA3D0[0], 0, 1;
- %load/v 32, V_$006D8E20[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DA0A8[0], 0, 32;
- %assign V_$006DA450[0], 0, 0;
- %assign V_$006D78C0[0], 0, 1;
- %assign V_$006D78C0[1], 0, 0;
- %assign V_$006D78C0[2], 0, 1;
- %assign V_$006D78C0[3], 0, 0;
- %jmp T_22.14;
-T_22.6 ;
- %assign V_$006DA3D0[0], 0, 0;
- %assign V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[1], 0, 1;
- %assign V_$006D78C0[2], 0, 1;
- %assign V_$006D78C0[3], 0, 0;
- %jmp T_22.14;
-T_22.7 ;
- %load 32, V_$006DACE0[0];
- %jmp/0xz T_22.23, 32;
- %ix/load 0, 3;
- %assign/v0 V_$006D78C0[0], 0, 1;
- %assign V_$006D78C0[3], 0, 0;
- %assign V_$006DA450[0], 0, 1;
-T_22.23 ;
- %jmp T_22.14;
-T_22.8 ;
- %load 32, V_$006DAB98[0];
- %load 33, V_$006DA998[0];
- %load 34, V_$006DA998[1];
- %load 35, V_$006DA998[2];
- %load 36, V_$006DA998[3];
- %load 37, V_$006DA998[4];
- %load 38, V_$006DA998[5];
- %load 39, V_$006DA998[6];
- %load 40, V_$006DA998[7];
- %cmpi/u 33, 1, 8;
- %inv 4, 1;
- %mov 33, 4, 1;
- %or 32, 33, 1;
- %load/v 33, V_$006D8E20[0], 8;
- %cmpi/u 33, 255, 8;
- %inv 4, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_22.25, 32;
- %assign V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[1], 0, 0;
- %assign V_$006D78C0[2], 0, 1;
- %assign V_$006D78C0[3], 0, 0;
- %jmp T_22.26;
-T_22.25 ;
- %load 32, V_$006DAB98[0];
- %load 33, V_$006DA998[0];
- %load 34, V_$006DA998[1];
- %load 35, V_$006DA998[2];
- %load 36, V_$006DA998[3];
- %load 37, V_$006DA998[4];
- %load 38, V_$006DA998[5];
- %load 39, V_$006DA998[6];
- %load 40, V_$006DA998[7];
- %cmpi/u 33, 1, 8;
- %inv 4, 1;
- %mov 33, 4, 1;
- %or 32, 33, 1;
- %jmp/0xz T_22.27, 32;
- %assign V_$006D78C0[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D78C0[1], 0, 0;
- %assign V_$006D9D58[0], 0, 1;
- %assign V_$006D9D58[1], 0, 0;
- %jmp T_22.28;
-T_22.27 ;
- %assign V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[1], 0, 1;
- %assign V_$006D78C0[2], 0, 0;
- %assign V_$006D78C0[3], 0, 1;
-T_22.28 ;
-T_22.26 ;
- %jmp T_22.14;
-T_22.9 ;
- %load 32, V_$006DACE0[0];
- %jmp/0xz T_22.29, 32;
- %assign V_$006D78C0[0], 0, 1;
- %assign V_$006D78C0[1], 0, 0;
- %assign V_$006D78C0[2], 0, 0;
- %assign V_$006D78C0[3], 0, 1;
- %assign V_$006DA450[0], 0, 1;
-T_22.29 ;
- %jmp T_22.14;
-T_22.10 ;
- %load 32, V_$006DAB98[0];
- %load 33, V_$006DA998[0];
- %load 34, V_$006DA998[1];
- %load 35, V_$006DA998[2];
- %load 36, V_$006DA998[3];
- %load 37, V_$006DA998[4];
- %load 38, V_$006DA998[5];
- %load 39, V_$006DA998[6];
- %load 40, V_$006DA998[7];
- %cmpi/u 33, 0, 8;
- %inv 4, 1;
- %mov 33, 4, 1;
- %or 32, 33, 1;
- %load/v 33, V_$006D8E20[0], 8;
- %cmpi/u 33, 255, 8;
- %inv 4, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_22.31, 32;
- %assign V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[1], 0, 1;
- %assign V_$006D78C0[2], 0, 0;
- %assign V_$006D78C0[3], 0, 1;
- %jmp T_22.32;
-T_22.31 ;
- %load 32, V_$006DAB98[0];
- %load 33, V_$006DA998[0];
- %load 34, V_$006DA998[1];
- %load 35, V_$006DA998[2];
- %load 36, V_$006DA998[3];
- %load 37, V_$006DA998[4];
- %load 38, V_$006DA998[5];
- %load 39, V_$006DA998[6];
- %load 40, V_$006DA998[7];
- %cmpi/u 33, 0, 8;
- %inv 4, 1;
- %mov 33, 4, 1;
- %or 32, 33, 1;
- %jmp/0xz T_22.33, 32;
- %assign V_$006D78C0[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D78C0[1], 0, 0;
- %assign V_$006D9D58[0], 0, 0;
- %assign V_$006D9D58[1], 0, 1;
- %jmp T_22.34;
-T_22.33 ;
- %assign V_$006D78C0[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D78C0[1], 0, 0;
-T_22.34 ;
-T_22.32 ;
- %jmp T_22.14;
-T_22.11 ;
- %assign V_$006D8900[0], 0, 1;
- %ix/load 0, 5;
- %assign/v0 V_$006D8900[1], 0, 0;
- %assign V_$006D8900[6], 0, 1;
- %assign V_$006D8900[7], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D8B78[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D90D8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D93B8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D9F90[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D85E0[0], 0, 1;
- %assign V_$006DA3D0[0], 0, 1;
- %load/v 32, V_$006D8E20[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DA0A8[0], 0, 32;
- %assign V_$006DA450[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D9750[0], 0, 0;
- %assign V_$006D78C0[0], 0, 1;
- %assign V_$006D78C0[1], 0, 1;
- %assign V_$006D78C0[2], 0, 0;
- %assign V_$006D78C0[3], 0, 1;
- %jmp T_22.14;
-T_22.12 ;
- %load/v 32, V_$006D83C0[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D9750[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006D9AB8[0], 0, 0;
- %assign V_$006DA3D0[0], 0, 0;
- %load/v 32, V_$006D83C0[0], 10;
- %cmpi/u 32, 375, 10;
- %jmp/0xz T_22.35, 4;
- %ix/load 0, 3;
- %assign/v0 V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[3], 0, 1;
- %jmp T_22.36;
-T_22.35 ;
- %assign V_$006D78C0[0], 0, 0;
- %assign V_$006D78C0[1], 0, 0;
- %assign V_$006D78C0[2], 0, 1;
- %assign V_$006D78C0[3], 0, 1;
-T_22.36 ;
- %jmp T_22.14;
-T_22.13 ;
- %load/v 32, V_$006D83F8[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D9AB8[0], 0, 32;
- %load/v 32, V_$006D83F8[0], 8;
- %cmpi/u 32, 255, 8;
- %jmp/0xz T_22.37, 4;
- %assign V_$006D78C0[0], 0, 1;
- %assign V_$006D78C0[1], 0, 1;
- %assign V_$006D78C0[2], 0, 0;
- %assign V_$006D78C0[3], 0, 1;
-T_22.37 ;
- %jmp T_22.14;
-T_22.14 ;
- %jmp T_22;
- .thread T_22, $push;
- .scope S_006D5E10;
-T_23 ;
- %wait E_003DE478;
- %load 32, V_$006DAC00[0];
- %jmp/0xz T_23.0, 32;
- %ix/load 0, 4;
- %assign/v0 V_$006D7810[0], 0, 0;
- %jmp T_23.1;
-T_23.0 ;
- %load/v 32, V_$006D78C0[0], 4;
- %ix/load 0, 4;
- %assign/v0 V_$006D7810[0], 0, 32;
-T_23.1 ;
- %jmp T_23;
- .thread T_23;
- .scope S_006D5E10;
-T_24 ;
- %wait E_003DE478;
- %load 32, V_$006DAC00[0];
- %jmp/0xz T_24.0, 32;
- %load 32, V_$006DAE30[0];
- %load 33, V_$006DAE30[1];
- %load 34, V_$006DAE30[2];
- %load 35, V_$006DAE30[3];
- %load 36, V_$006DAE30[4];
- %load 37, V_$006DAE30[5];
- %load 38, V_$006DAE30[6];
- %load 39, V_$006DAE30[7];
- %ix/load 0, 8;
- %assign/v0 V_$006DB188[0], 0, 32;
- %assign V_$006D7E68[0], 0, 0;
- %assign V_$006DADF8[0], 0, 1;
- %assign V_$006D8260[0], 0, 0;
- %assign V_$006D8260[1], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D71D0[0], 0, 0;
- %assign V_$006DB4B8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D7B08[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D7C70[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D7DD0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D80C8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D8228[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D7F80[0], 0, 0;
- %assign V_$006DAD18[0], 0, 0;
- %assign V_$006DACA8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D8E20[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D83C0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D83F8[0], 0, 0;
- %jmp T_24.1;
-T_24.0 ;
- %load/v 32, V_$006DA4D0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006DB188[0], 0, 32;
- %load/v 32, V_$006D8560[0], 1;
- %assign V_$006D7E68[0], 0, 32;
- %load/v 32, V_$006DA450[0], 1;
- %assign V_$006DADF8[0], 0, 32;
- %load/v 32, V_$006D9D58[0], 2;
- %assign V_$006D8260[0], 0, 32;
- %assign V_$006D8260[1], 0, 33;
- %load/v 32, V_$006DA638[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D71D0[0], 0, 32;
- %load/v 32, V_$006DA918[0], 1;
- %assign V_$006DB4B8[0], 0, 32;
- %load/v 32, V_$006D8900[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D7B08[0], 0, 32;
- %load/v 32, V_$006D8B78[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D7C70[0], 0, 32;
- %load/v 32, V_$006D90D8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D7DD0[0], 0, 32;
- %load/v 32, V_$006D93B8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D80C8[0], 0, 32;
- %load/v 32, V_$006D9F90[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D8228[0], 0, 32;
- %load/v 32, V_$006D85E0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D7F80[0], 0, 32;
- %load/v 32, V_$006DA3D0[0], 1;
- %assign V_$006DAD18[0], 0, 32;
- %load/v 32, V_$006DA348[0], 1;
- %assign V_$006DACA8[0], 0, 32;
- %load/v 32, V_$006DA0A8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D8E20[0], 0, 32;
- %load/v 32, V_$006D9750[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D83C0[0], 0, 32;
- %load/v 32, V_$006D9AB8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D83F8[0], 0, 32;
-T_24.1 ;
- %jmp T_24;
- .thread T_24;
- .scope S_006D0E50;
-T_25 ;
- %wait E_006D1810;
- %load/v 32, V_$006D1830[0], 6;
- %ix/load 0, 6;
- %assign/v0 V_$006D1C70[0], 0, 32;
- %load/v 32, V_$006D6E38[0], 1;
- %assign V_$006D5F20[0], 0, 32;
- %load/v 32, V_$006D6C70[0], 1;
- %assign V_$006D5948[0], 0, 32;
- %load/v 32, V_$006D6488[0], 2;
- %assign V_$006D5DD8[0], 0, 32;
- %assign V_$006D5DD8[1], 0, 33;
- %load/v 32, V_$006D75E8[0], 2;
- %assign V_$006D63B0[0], 0, 32;
- %assign V_$006D63B0[1], 0, 33;
- %load/v 32, V_$006D7208[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 32;
- %load/v 32, V_$006D72A8[0], 1;
- %assign V_$006D62B0[0], 0, 32;
- %load/v 32, V_$006D6920[0], 1;
- %assign V_$006D5FB0[0], 0, 32;
- %load/v 32, V_$006D2970[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D3890[0], 0, 32;
- %load/v 32, V_$006D2AB0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D3B18[0], 0, 32;
- %load/v 32, V_$006D2C18[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D40D8[0], 0, 32;
- %load/v 32, V_$006D2D78[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D43B8[0], 0, 32;
- %load/v 32, V_$006D3138[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D4F90[0], 0, 32;
- %load/v 32, V_$006D2790[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D3580[0], 0, 32;
- %load/v 32, V_$006D6C38[0], 1;
- %assign V_$006D5880[0], 0, 32;
- %load/v 32, V_$006D32B0[0], 9;
- %ix/load 0, 9;
- %assign/v0 V_$006D5200[0], 0, 32;
- %load/v 32, V_$006D3278[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D4750[0], 0, 32;
- %load/v 32, V_$006D3310[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D4A70[0], 0, 32;
- %load/v 32, V_$006D7488[0], 1;
- %assign V_$006D6330[0], 0, 32;
- %load/v 32, V_$006D6B90[0], 1;
- %assign V_$006D5800[0], 0, 32;
- %load/v 32, V_$006D6958[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D5520[0], 0, 32;
- %load/v 32, V_$006D6CA8[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D5A20[0], 0, 32;
- %load/v 32, V_$006D3370[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D4D10[0], 0, 32;
- %load/v 32, V_$006D1830[0], 6;
- %cmpi/u 32, 0, 6;
- %jmp/1 T_25.0, 6;
- %cmpi/u 32, 4, 6;
- %jmp/1 T_25.1, 6;
- %cmpi/u 32, 1, 6;
- %jmp/1 T_25.2, 6;
- %cmpi/u 32, 2, 6;
- %jmp/1 T_25.3, 6;
- %cmpi/u 32, 3, 6;
- %jmp/1 T_25.4, 6;
- %cmpi/u 32, 5, 6;
- %jmp/1 T_25.5, 6;
- %cmpi/u 32, 6, 6;
- %jmp/1 T_25.6, 6;
- %cmpi/u 32, 7, 6;
- %jmp/1 T_25.7, 6;
- %cmpi/u 32, 8, 6;
- %jmp/1 T_25.8, 6;
- %cmpi/u 32, 9, 6;
- %jmp/1 T_25.9, 6;
- %cmpi/u 32, 10, 6;
- %jmp/1 T_25.10, 6;
- %cmpi/u 32, 40, 6;
- %jmp/1 T_25.11, 6;
- %cmpi/u 32, 41, 6;
- %jmp/1 T_25.12, 6;
- %cmpi/u 32, 42, 6;
- %jmp/1 T_25.13, 6;
- %cmpi/u 32, 43, 6;
- %jmp/1 T_25.14, 6;
- %cmpi/u 32, 44, 6;
- %jmp/1 T_25.15, 6;
- %cmpi/u 32, 45, 6;
- %jmp/1 T_25.16, 6;
- %cmpi/u 32, 23, 6;
- %jmp/1 T_25.17, 6;
- %cmpi/u 32, 24, 6;
- %jmp/1 T_25.18, 6;
- %cmpi/u 32, 25, 6;
- %jmp/1 T_25.19, 6;
- %cmpi/u 32, 26, 6;
- %jmp/1 T_25.20, 6;
- %cmpi/u 32, 27, 6;
- %jmp/1 T_25.21, 6;
- %cmpi/u 32, 28, 6;
- %jmp/1 T_25.22, 6;
- %cmpi/u 32, 29, 6;
- %jmp/1 T_25.23, 6;
- %cmpi/u 32, 30, 6;
- %jmp/1 T_25.24, 6;
- %cmpi/u 32, 31, 6;
- %jmp/1 T_25.25, 6;
- %cmpi/u 32, 46, 6;
- %jmp/1 T_25.26, 6;
- %cmpi/u 32, 32, 6;
- %jmp/1 T_25.27, 6;
- %cmpi/u 32, 33, 6;
- %jmp/1 T_25.28, 6;
- %cmpi/u 32, 34, 6;
- %jmp/1 T_25.29, 6;
- %cmpi/u 32, 35, 6;
- %jmp/1 T_25.30, 6;
- %cmpi/u 32, 36, 6;
- %jmp/1 T_25.31, 6;
- %cmpi/u 32, 37, 6;
- %jmp/1 T_25.32, 6;
- %cmpi/u 32, 38, 6;
- %jmp/1 T_25.33, 6;
- %cmpi/u 32, 39, 6;
- %jmp/1 T_25.34, 6;
- %cmpi/u 32, 11, 6;
- %jmp/1 T_25.35, 6;
- %cmpi/u 32, 12, 6;
- %jmp/1 T_25.36, 6;
- %cmpi/u 32, 13, 6;
- %jmp/1 T_25.37, 6;
- %cmpi/u 32, 14, 6;
- %jmp/1 T_25.38, 6;
- %cmpi/u 32, 15, 6;
- %jmp/1 T_25.39, 6;
- %cmpi/u 32, 16, 6;
- %jmp/1 T_25.40, 6;
- %cmpi/u 32, 17, 6;
- %jmp/1 T_25.41, 6;
- %cmpi/u 32, 18, 6;
- %jmp/1 T_25.42, 6;
- %cmpi/u 32, 19, 6;
- %jmp/1 T_25.43, 6;
- %cmpi/u 32, 20, 6;
- %jmp/1 T_25.44, 6;
- %cmpi/u 32, 21, 6;
- %jmp/1 T_25.45, 6;
- %cmpi/u 32, 22, 6;
- %jmp/1 T_25.46, 6;
- %cmpi/u 32, 47, 6;
- %jmp/1 T_25.47, 6;
- %jmp T_25.48;
-T_25.0 ;
- %assign V_$006D5F20[0], 0, 0;
- %assign V_$006D5948[0], 0, 1;
- %assign V_$006D5DD8[0], 0, 0;
- %assign V_$006D5DD8[1], 0, 0;
- %assign V_$006D63B0[0], 0, 0;
- %assign V_$006D63B0[1], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 0;
- %assign V_$006D62B0[0], 0, 0;
- %assign V_$006D5FB0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D3890[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D3B18[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D40D8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D43B8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D4F90[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D3580[0], 0, 0;
- %assign V_$006D5880[0], 0, 0;
- %ix/load 0, 9;
- %assign/v0 V_$006D5200[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D4750[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D4A70[0], 0, 0;
- %assign V_$006D5DD8[0], 0, 0;
- %assign V_$006D5DD8[1], 0, 0;
- %assign V_$006D63B0[0], 0, 0;
- %assign V_$006D63B0[1], 0, 0;
- %assign V_$006D6330[0], 0, 0;
- %assign V_$006D5800[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D5520[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D5A20[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D4D10[0], 0, 0;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
- %jmp T_25.48;
-T_25.1 ;
- %assign V_$006D5948[0], 0, 1;
- %assign V_$006D5F20[0], 0, 1;
- %load 32, V_$006D6EC0[0];
- %load 33, V_$006D6EC0[1];
- %cmpi/u 32, 2, 2;
- %jmp/0xz T_25.49, 4;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %assign V_$006D5948[0], 0, 0;
- %assign V_$006D5F20[0], 0, 0;
- %assign V_$006D5DD8[0], 0, 0;
- %assign V_$006D5DD8[1], 0, 0;
- %jmp T_25.50;
-T_25.49 ;
- %load 32, V_$006D6EC0[0];
- %load 33, V_$006D6EC0[1];
- %cmpi/u 32, 1, 2;
- %jmp/0xz T_25.51, 4;
- %assign V_$006D1C70[0], 0, 1;
- %ix/load 0, 5;
- %assign/v0 V_$006D1C70[1], 0, 0;
- %assign V_$006D5948[0], 0, 0;
- %assign V_$006D5F20[0], 0, 0;
- %assign V_$006D63B0[0], 0, 0;
- %assign V_$006D63B0[1], 0, 0;
-T_25.51 ;
-T_25.50 ;
- %jmp T_25.48;
-T_25.2 ;
- %ix/load 0, 3;
- %assign/v0 V_$006D3890[0], 0, 0;
- %assign V_$006D3890[3], 0, 1;
- %assign V_$006D3890[4], 0, 1;
- %assign V_$006D3890[5], 0, 0;
- %assign V_$006D3890[6], 0, 1;
- %assign V_$006D3890[7], 0, 0;
- %load 32, V_$006D2078[24];
- %load 33, V_$006D2078[25];
- %load 34, V_$006D2078[26];
- %load 35, V_$006D2078[27];
- %load 36, V_$006D2078[28];
- %load 37, V_$006D2078[29];
- %load 38, V_$006D2078[30];
- %load 39, V_$006D2078[31];
- %ix/load 0, 8;
- %assign/v0 V_$006D3B18[0], 0, 32;
- %load 32, V_$006D2078[16];
- %load 33, V_$006D2078[17];
- %load 34, V_$006D2078[18];
- %load 35, V_$006D2078[19];
- %load 36, V_$006D2078[20];
- %load 37, V_$006D2078[21];
- %load 38, V_$006D2078[22];
- %load 39, V_$006D2078[23];
- %ix/load 0, 8;
- %assign/v0 V_$006D40D8[0], 0, 32;
- %load 32, V_$006D2078[8];
- %load 33, V_$006D2078[9];
- %load 34, V_$006D2078[10];
- %load 35, V_$006D2078[11];
- %load 36, V_$006D2078[12];
- %load 37, V_$006D2078[13];
- %load 38, V_$006D2078[14];
- %load 39, V_$006D2078[15];
- %ix/load 0, 8;
- %assign/v0 V_$006D43B8[0], 0, 32;
- %load 32, V_$006D2078[0];
- %load 33, V_$006D2078[1];
- %load 34, V_$006D2078[2];
- %load 35, V_$006D2078[3];
- %load 36, V_$006D2078[4];
- %load 37, V_$006D2078[5];
- %load 38, V_$006D2078[6];
- %load 39, V_$006D2078[7];
- %ix/load 0, 8;
- %assign/v0 V_$006D4F90[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006D3580[0], 0, 1;
- %assign V_$006D5880[0], 0, 1;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 1;
- %ix/load 0, 4;
- %assign/v0 V_$006D1C70[2], 0, 0;
- %jmp T_25.48;
-T_25.3 ;
- %load 32, V_$006D6C00[0];
- %load 33, V_$006D6648[0];
- %load 34, V_$006D6F98[0];
- %load 35, V_$006D6F98[1];
- %load 36, V_$006D6F98[2];
- %load 37, V_$006D6F98[3];
- %load 38, V_$006D6F98[4];
- %load 39, V_$006D6F98[5];
- %load 40, V_$006D6F98[6];
- %load 41, V_$006D6F98[7];
- %cmpi/u 34, 0, 8;
- %inv 4, 1;
- %mov 34, 4, 1;
- %or 33, 34, 1;
- %and 32, 33, 1;
- %jmp/0xz T_25.53, 32;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
- %assign V_$006D63B0[0], 0, 1;
- %assign V_$006D63B0[1], 0, 0;
- %jmp T_25.54;
-T_25.53 ;
- %load 32, V_$006D6C00[0];
- %jmp/0xz T_25.55, 32;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
-T_25.55 ;
-T_25.54 ;
- %jmp T_25.48;
-T_25.4 ;
- %assign V_$006D5880[0], 0, 0;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %ix/load 0, 4;
- %assign/v0 V_$006D1C70[2], 0, 0;
- %jmp T_25.48;
-T_25.5 ;
- %assign V_$006D62B0[0], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.6 ;
- %load 32, V_$006D7198[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_25.57, 4;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
-T_25.57 ;
- %jmp T_25.48;
-T_25.7 ;
- %assign V_$006D62B0[0], 0, 0;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.8 ;
- %load 32, V_$006D7198[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_25.59, 4;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
-T_25.59 ;
- %jmp T_25.48;
-T_25.9 ;
- %assign V_$006D62B0[0], 0, 0;
- %ix/load 0, 4;
- %assign/v0 V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.10 ;
- %load 32, V_$006D7198[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_25.61, 4;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
- %assign V_$006D6008[0], 0, 0;
- %ix/load 0, 7;
- %assign/v0 V_$006D6008[1], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
-T_25.61 ;
- %jmp T_25.48;
-T_25.11 ;
- %load/v 32, V_$006D3370[0], 8;
- %cmpi/u 32, 0, 8;
- %mov 32, 4, 1;
- %load/v 33, V_$006D6CA8[0], 10;
- %cmpi/u 33, 182, 10;
- %inv 4, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_25.63, 32;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %load/v 32, V_$006D6CA8[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D5A20[0], 0, 32;
- %jmp T_25.64;
-T_25.63 ;
- %load/v 32, V_$006D6CA8[0], 10;
- %cmpi/u 32, 182, 10;
- %jmp/0xz T_25.65, 4;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
- %assign V_$006D63B0[0], 0, 1;
- %assign V_$006D63B0[1], 0, 1;
- %jmp T_25.66;
-T_25.65 ;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
-T_25.66 ;
-T_25.64 ;
- %jmp T_25.48;
-T_25.12 ;
- %load 32, V_$006D68B8[0];
- %jmp/0xz T_25.67, 32;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %load 32, V_$006D66D8[0];
- %load 33, V_$006D66D8[1];
- %load 34, V_$006D66D8[2];
- %load 35, V_$006D66D8[3];
- %load 36, V_$006D66D8[4];
- %load 37, V_$006D66D8[5];
- %load 38, V_$006D66D8[6];
- %load 39, V_$006D66D8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006D4D10[0], 0, 32;
-T_25.67 ;
- %jmp T_25.48;
-T_25.13 ;
- %assign V_$006D62B0[0], 0, 0;
- %assign V_$006D5FB0[0], 0, 0;
- %load/v 32, V_$006D3278[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D4750[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006D4A70[0], 0, 0;
- %load/v 32, V_$006D3278[0], 8;
- %cmpi/u 32, 255, 8;
- %jmp/0xz T_25.69, 4;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %jmp T_25.70;
-T_25.69 ;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
-T_25.70 ;
- %jmp T_25.48;
-T_25.14 ;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
- %assign V_$006D5FB0[0], 0, 1;
- %ix/load 0, 8;
- %assign/v0 V_$006D4750[0], 0, 0;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %jmp T_25.48;
-T_25.15 ;
- %load/v 32, V_$006D3310[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D4A70[0], 0, 32;
- %load/v 32, V_$006D3310[0], 8;
- %cmpi/u 32, 255, 8;
- %jmp/0xz T_25.71, 4;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
-T_25.71 ;
- %jmp T_25.48;
-T_25.16 ;
- %ix/load 0, 10;
- %assign/v0 V_$006D5A20[0], 0, 0;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %jmp T_25.48;
-T_25.17 ;
- %assign V_$006D3890[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D3890[1], 0, 0;
- %assign V_$006D3890[4], 0, 1;
- %assign V_$006D3890[5], 0, 0;
- %assign V_$006D3890[6], 0, 1;
- %assign V_$006D3890[7], 0, 0;
- %load 32, V_$006D2078[24];
- %load 33, V_$006D2078[25];
- %load 34, V_$006D2078[26];
- %load 35, V_$006D2078[27];
- %load 36, V_$006D2078[28];
- %load 37, V_$006D2078[29];
- %load 38, V_$006D2078[30];
- %load 39, V_$006D2078[31];
- %ix/load 0, 8;
- %assign/v0 V_$006D3B18[0], 0, 32;
- %load 32, V_$006D2078[16];
- %load 33, V_$006D2078[17];
- %load 34, V_$006D2078[18];
- %load 35, V_$006D2078[19];
- %load 36, V_$006D2078[20];
- %load 37, V_$006D2078[21];
- %load 38, V_$006D2078[22];
- %load 39, V_$006D2078[23];
- %ix/load 0, 8;
- %assign/v0 V_$006D40D8[0], 0, 32;
- %load 32, V_$006D2078[8];
- %load 33, V_$006D2078[9];
- %load 34, V_$006D2078[10];
- %load 35, V_$006D2078[11];
- %load 36, V_$006D2078[12];
- %load 37, V_$006D2078[13];
- %load 38, V_$006D2078[14];
- %load 39, V_$006D2078[15];
- %ix/load 0, 8;
- %assign/v0 V_$006D43B8[0], 0, 32;
- %load 32, V_$006D2078[0];
- %load 33, V_$006D2078[1];
- %load 34, V_$006D2078[2];
- %load 35, V_$006D2078[3];
- %load 36, V_$006D2078[4];
- %load 37, V_$006D2078[5];
- %load 38, V_$006D2078[6];
- %load 39, V_$006D2078[7];
- %ix/load 0, 8;
- %assign/v0 V_$006D4F90[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006D3580[0], 0, 1;
- %assign V_$006D5880[0], 0, 1;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.18 ;
- %load 32, V_$006D6C00[0];
- %load 33, V_$006D6648[0];
- %load 34, V_$006D6F98[0];
- %load 35, V_$006D6F98[1];
- %load 36, V_$006D6F98[2];
- %load 37, V_$006D6F98[3];
- %load 38, V_$006D6F98[4];
- %load 39, V_$006D6F98[5];
- %load 40, V_$006D6F98[6];
- %load 41, V_$006D6F98[7];
- %cmpi/u 34, 0, 8;
- %inv 4, 1;
- %mov 34, 4, 1;
- %or 33, 34, 1;
- %and 32, 33, 1;
- %jmp/0xz T_25.73, 32;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
- %assign V_$006D5DD8[0], 0, 1;
- %assign V_$006D5DD8[1], 0, 0;
- %jmp T_25.74;
-T_25.73 ;
- %load 32, V_$006D6C00[0];
- %jmp/0xz T_25.75, 32;
- %assign V_$006D1C70[0], 0, 0;
- %ix/load 0, 4;
- %assign/v0 V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
-T_25.75 ;
-T_25.74 ;
- %jmp T_25.48;
-T_25.19 ;
- %assign V_$006D5880[0], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.20 ;
- %load/v 32, V_$006D3370[0], 8;
- %cmpi/u 32, 254, 8;
- %inv 4, 1;
- %mov 32, 4, 1;
- %load/v 33, V_$006D6CA8[0], 10;
- %cmpi/u 33, 72, 10;
- %inv 4, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_25.77, 32;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %load/v 32, V_$006D6CA8[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D5A20[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006D4750[0], 0, 0;
- %jmp T_25.78;
-T_25.77 ;
- %load/v 32, V_$006D6CA8[0], 10;
- %cmpi/u 32, 72, 10;
- %jmp/0xz T_25.79, 4;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
- %assign V_$006D5DD8[0], 0, 0;
- %assign V_$006D5DD8[1], 0, 1;
- %jmp T_25.80;
-T_25.79 ;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %assign V_$006D5FB0[0], 0, 1;
-T_25.80 ;
-T_25.78 ;
- %jmp T_25.48;
-T_25.21 ;
- %load 32, V_$006D68B8[0];
- %jmp/0xz T_25.81, 32;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %load 32, V_$006D66D8[0];
- %load 33, V_$006D66D8[1];
- %load 34, V_$006D66D8[2];
- %load 35, V_$006D66D8[3];
- %load 36, V_$006D66D8[4];
- %load 37, V_$006D66D8[5];
- %load 38, V_$006D66D8[6];
- %load 39, V_$006D66D8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006D4D10[0], 0, 32;
-T_25.81 ;
- %jmp T_25.48;
-T_25.22 ;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
- %assign V_$006D5FB0[0], 0, 1;
- %ix/load 0, 5;
- %assign/v0 V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.23 ;
- %load/v 32, V_$006D3278[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D4750[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006D4A70[0], 0, 0;
- %load/v 32, V_$006D3278[0], 8;
- %cmpi/u 32, 255, 8;
- %jmp/0xz T_25.83, 4;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.84;
-T_25.83 ;
- %assign V_$006D1C70[0], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
-T_25.84 ;
- %jmp T_25.48;
-T_25.24 ;
- %ix/load 0, 10;
- %assign/v0 V_$006D5A20[0], 0, 0;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.25 ;
- %assign V_$006D62B0[0], 0, 0;
- %assign V_$006D5FB0[0], 0, 0;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.26 ;
- %load/v 32, V_$006D3310[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D4A70[0], 0, 32;
- %load/v 32, V_$006D3310[0], 8;
- %cmpi/u 32, 255, 8;
- %jmp/0xz T_25.85, 4;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
-T_25.85 ;
- %jmp T_25.48;
-T_25.27 ;
- %assign V_$006D62B0[0], 0, 1;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %load/v 32, V_$006D32B0[0], 9;
- %addi 32, 1, 9;
- %ix/load 0, 9;
- %assign/v0 V_$006D5200[0], 0, 32;
- %assign V_$006D1C70[0], 0, 1;
- %ix/load 0, 4;
- %assign/v0 V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %jmp T_25.48;
-T_25.28 ;
- %assign V_$006D62B0[0], 0, 0;
- %load 32, V_$006D68B8[0];
- %jmp/0xz T_25.87, 32;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %assign V_$006D5800[0], 0, 1;
- %assign V_$006D5FB0[0], 0, 1;
- %load 32, V_$006D66D8[0];
- %load 33, V_$006D66D8[1];
- %load 34, V_$006D66D8[2];
- %load 35, V_$006D66D8[3];
- %load 36, V_$006D66D8[4];
- %load 37, V_$006D66D8[5];
- %load 38, V_$006D66D8[6];
- %load 39, V_$006D66D8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006D5520[0], 0, 32;
-T_25.87 ;
- %jmp T_25.48;
-T_25.29 ;
- %load/v 32, V_$006D32B0[0], 9;
- %cmpi/u 32, 0, 9;
- %jmp/0xz T_25.89, 4;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %assign V_$006D5FB0[0], 0, 0;
- %assign V_$006D5800[0], 0, 0;
- %jmp T_25.90;
-T_25.89 ;
- %ix/load 0, 5;
- %assign/v0 V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %assign V_$006D5FB0[0], 0, 0;
- %assign V_$006D5800[0], 0, 0;
-T_25.90 ;
- %jmp T_25.48;
-T_25.30 ;
- %ix/load 0, 5;
- %assign/v0 V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %assign V_$006D5FB0[0], 0, 0;
- %ix/load 0, 9;
- %assign/v0 V_$006D5200[0], 0, 0;
- %jmp T_25.48;
-T_25.31 ;
- %assign V_$006D62B0[0], 0, 0;
- %load 32, V_$006D7160[0];
- %jmp/0xz T_25.91, 32;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
-T_25.91 ;
- %jmp T_25.48;
-T_25.32 ;
- %assign V_$006D62B0[0], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %jmp T_25.48;
-T_25.33 ;
- %load 32, V_$006D7198[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_25.93, 4;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
-T_25.93 ;
- %jmp T_25.48;
-T_25.34 ;
- %load 32, V_$006D7198[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_25.95, 4;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
-T_25.95 ;
- %jmp T_25.48;
-T_25.35 ;
- %assign V_$006D62B0[0], 0, 0;
- %load/v 32, V_$006D32B0[0], 9;
- %cmpi/u 32, 0, 9;
- %jmp/0xz T_25.97, 4;
- %ix/load 0, 4;
- %assign/v0 V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.98;
-T_25.97 ;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
-T_25.98 ;
- %jmp T_25.48;
-T_25.36 ;
- %load 32, V_$006D7198[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_25.99, 4;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
- %load 32, V_$006D73E8[0];
- %load 33, V_$006D73E8[1];
- %load 34, V_$006D73E8[2];
- %load 35, V_$006D73E8[3];
- %load 36, V_$006D73E8[4];
- %load 37, V_$006D73E8[5];
- %load 38, V_$006D73E8[6];
- %load 39, V_$006D73E8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 32;
- %assign V_$006D62B0[0], 0, 1;
-T_25.99 ;
- %jmp T_25.48;
-T_25.37 ;
- %assign V_$006D6330[0], 0, 1;
- %load/v 32, V_$006D32B0[0], 9;
- %addi 32, 1, 9;
- %ix/load 0, 9;
- %assign/v0 V_$006D5200[0], 0, 32;
- %assign V_$006D1C70[0], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.38 ;
- %assign V_$006D6330[0], 0, 0;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.39 ;
- %ix/load 0, 9;
- %assign/v0 V_$006D5200[0], 0, 0;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.40 ;
- %load 32, V_$006D7198[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_25.101, 4;
- %assign V_$006D1C70[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
-T_25.101 ;
- %jmp T_25.48;
-T_25.41 ;
- %assign V_$006D62B0[0], 0, 0;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %jmp T_25.48;
-T_25.42 ;
- %assign V_$006D62B0[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D5A20[0], 0, 0;
- %load 32, V_$006D7160[0];
- %jmp/0xz T_25.103, 32;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
-T_25.103 ;
- %jmp T_25.48;
-T_25.43 ;
- %load 32, V_$006D7198[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_25.105, 4;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 0;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
-T_25.105 ;
- %jmp T_25.48;
-T_25.44 ;
- %load/v 32, V_$006D6CA8[0], 10;
- %cmpi/u 32, 512, 10;
- %jmp/0xz T_25.107, 4;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006D1C70[3], 0, 0;
- %assign V_$006D63B0[0], 0, 0;
- %assign V_$006D63B0[1], 0, 1;
- %jmp T_25.108;
-T_25.107 ;
- %load/v 32, V_$006D3370[0], 5;
- %cmpi/u 32, 5, 5;
- %jmp/0xz T_25.109, 4;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %jmp T_25.110;
-T_25.109 ;
- %assign V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
-T_25.110 ;
-T_25.108 ;
- %jmp T_25.48;
-T_25.45 ;
- %ix/load 0, 4;
- %assign/v0 V_$006D1C70[0], 0, 1;
- %assign V_$006D1C70[4], 0, 0;
- %assign V_$006D1C70[5], 0, 1;
- %ix/load 0, 8;
- %assign/v0 V_$006D6008[0], 0, 1;
- %assign V_$006D62B0[0], 0, 1;
- %load/v 32, V_$006D6CA8[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D5A20[0], 0, 32;
- %assign V_$006D5FB0[0], 0, 1;
- %jmp T_25.48;
-T_25.46 ;
- %load 32, V_$006D68B8[0];
- %jmp/0xz T_25.111, 32;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 0;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %load 32, V_$006D66D8[0];
- %load 33, V_$006D66D8[1];
- %load 34, V_$006D66D8[2];
- %load 35, V_$006D66D8[3];
- %load 36, V_$006D66D8[4];
- %load 37, V_$006D66D8[5];
- %load 38, V_$006D66D8[6];
- %load 39, V_$006D66D8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006D4D10[0], 0, 32;
-T_25.111 ;
- %jmp T_25.48;
-T_25.47 ;
- %assign V_$006D1C70[0], 0, 0;
- %assign V_$006D1C70[1], 0, 1;
- %assign V_$006D1C70[2], 0, 1;
- %assign V_$006D1C70[3], 0, 0;
- %assign V_$006D1C70[4], 0, 1;
- %assign V_$006D1C70[5], 0, 0;
- %assign V_$006D62B0[0], 0, 0;
- %assign V_$006D5FB0[0], 0, 0;
- %jmp T_25.48;
-T_25.48 ;
- %jmp T_25;
- .thread T_25, $push;
- .scope S_006D0E50;
-T_26 ;
- %wait E_003DE478;
- %load 32, V_$006D66A0[0];
- %jmp/0xz T_26.0, 32;
- %ix/load 0, 6;
- %assign/v0 V_$006D1830[0], 0, 0;
- %jmp T_26.1;
-T_26.0 ;
- %load/v 32, V_$006D1C70[0], 6;
- %ix/load 0, 6;
- %assign/v0 V_$006D1830[0], 0, 32;
-T_26.1 ;
- %jmp T_26;
- .thread T_26;
- .scope S_006D0E50;
-T_27 ;
- %wait E_003DE478;
- %load 32, V_$006D66A0[0];
- %jmp/0xz T_27.0, 32;
- %assign V_$006D6E38[0], 0, 0;
- %assign V_$006D6C70[0], 0, 1;
- %assign V_$006D6488[0], 0, 0;
- %assign V_$006D6488[1], 0, 0;
- %assign V_$006D75E8[0], 0, 0;
- %assign V_$006D75E8[1], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D7208[0], 0, 0;
- %assign V_$006D72A8[0], 0, 0;
- %assign V_$006D6920[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D2970[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D2AB0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D2C18[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D2D78[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D3138[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D2790[0], 0, 0;
- %assign V_$006D6C38[0], 0, 0;
- %assign V_$006D7488[0], 0, 0;
- %assign V_$006D6B90[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D6958[0], 0, 0;
- %ix/load 0, 9;
- %assign/v0 V_$006D32B0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D3278[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D3310[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D6CA8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D3370[0], 0, 0;
- %jmp T_27.1;
-T_27.0 ;
- %load/v 32, V_$006D5F20[0], 1;
- %assign V_$006D6E38[0], 0, 32;
- %load/v 32, V_$006D5948[0], 1;
- %assign V_$006D6C70[0], 0, 32;
- %load/v 32, V_$006D5DD8[0], 2;
- %assign V_$006D6488[0], 0, 32;
- %assign V_$006D6488[1], 0, 33;
- %load/v 32, V_$006D63B0[0], 2;
- %assign V_$006D75E8[0], 0, 32;
- %assign V_$006D75E8[1], 0, 33;
- %load/v 32, V_$006D6008[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D7208[0], 0, 32;
- %load/v 32, V_$006D62B0[0], 1;
- %assign V_$006D72A8[0], 0, 32;
- %load/v 32, V_$006D5FB0[0], 1;
- %assign V_$006D6920[0], 0, 32;
- %load/v 32, V_$006D3890[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D2970[0], 0, 32;
- %load/v 32, V_$006D3B18[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D2AB0[0], 0, 32;
- %load/v 32, V_$006D40D8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D2C18[0], 0, 32;
- %load/v 32, V_$006D43B8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D2D78[0], 0, 32;
- %load/v 32, V_$006D4F90[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D3138[0], 0, 32;
- %load/v 32, V_$006D3580[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D2790[0], 0, 32;
- %load/v 32, V_$006D5880[0], 1;
- %assign V_$006D6C38[0], 0, 32;
- %load/v 32, V_$006D6330[0], 1;
- %assign V_$006D7488[0], 0, 32;
- %load/v 32, V_$006D5800[0], 1;
- %assign V_$006D6B90[0], 0, 32;
- %load/v 32, V_$006D5520[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D6958[0], 0, 32;
- %load/v 32, V_$006D5200[0], 9;
- %ix/load 0, 9;
- %assign/v0 V_$006D32B0[0], 0, 32;
- %load/v 32, V_$006D4750[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D3278[0], 0, 32;
- %load/v 32, V_$006D4A70[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D3310[0], 0, 32;
- %load/v 32, V_$006D5A20[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D6CA8[0], 0, 32;
- %load/v 32, V_$006D4D10[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D3370[0], 0, 32;
-T_27.1 ;
- %jmp T_27;
- .thread T_27;
- .scope S_006CC9E8;
-T_28 ;
- %wait E_006CCC00;
- %load 32, V_$006D13D0[0];
- %load 33, V_$006D1428[0];
- %or 32, 33, 1;
- %assign V_$006D1398[0], 0, 32;
- %jmp T_28;
- .thread T_28, $push;
- .scope S_006CC9E8;
-T_29 ;
- %wait E_003DE478;
- %load 32, V_$006CDA58[0];
- %load 33, V_$006CDA58[1];
- %load 34, V_$006CDA58[2];
- %load 35, V_$006CDA58[3];
- %load 36, V_$006CDA58[4];
- %load 37, V_$006CDA58[5];
- %load 38, V_$006CDA58[6];
- %load 39, V_$006CDA58[7];
- %load 40, V_$006CDCF8[0];
- %load 41, V_$006CDCF8[1];
- %load 42, V_$006CDCF8[2];
- %load 43, V_$006CDCF8[3];
- %load 44, V_$006CDCF8[4];
- %load 45, V_$006CDCF8[5];
- %load 46, V_$006CDCF8[6];
- %load 47, V_$006CDCF8[7];
- %or 32, 40, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CD788[0], 0, 32;
- %load 32, V_$006CE428[0];
- %load 33, V_$006CE428[1];
- %load 34, V_$006CE428[2];
- %load 35, V_$006CE428[3];
- %load 36, V_$006CE428[4];
- %load 37, V_$006CE428[5];
- %load 38, V_$006CE428[6];
- %load 39, V_$006CE428[7];
- %load 40, V_$006CE538[0];
- %load 41, V_$006CE538[1];
- %load 42, V_$006CE538[2];
- %load 43, V_$006CE538[3];
- %load 44, V_$006CE538[4];
- %load 45, V_$006CE538[5];
- %load 46, V_$006CE538[6];
- %load 47, V_$006CE538[7];
- %or 32, 40, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CE188[0], 0, 32;
- %load 32, V_$006CE460[0];
- %load 33, V_$006CE460[1];
- %load 34, V_$006CE460[2];
- %load 35, V_$006CE460[3];
- %load 36, V_$006CE460[4];
- %load 37, V_$006CE460[5];
- %load 38, V_$006CE460[6];
- %load 39, V_$006CE460[7];
- %load 40, V_$006CECD8[0];
- %load 41, V_$006CECD8[1];
- %load 42, V_$006CECD8[2];
- %load 43, V_$006CECD8[3];
- %load 44, V_$006CECD8[4];
- %load 45, V_$006CECD8[5];
- %load 46, V_$006CECD8[6];
- %load 47, V_$006CECD8[7];
- %or 32, 40, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CE7B0[0], 0, 32;
- %load 32, V_$006CF3F8[0];
- %load 33, V_$006CF3F8[1];
- %load 34, V_$006CF3F8[2];
- %load 35, V_$006CF3F8[3];
- %load 36, V_$006CF3F8[4];
- %load 37, V_$006CF3F8[5];
- %load 38, V_$006CF3F8[6];
- %load 39, V_$006CF3F8[7];
- %load 40, V_$006CFF80[0];
- %load 41, V_$006CFF80[1];
- %load 42, V_$006CFF80[2];
- %load 43, V_$006CFF80[3];
- %load 44, V_$006CFF80[4];
- %load 45, V_$006CFF80[5];
- %load 46, V_$006CFF80[6];
- %load 47, V_$006CFF80[7];
- %or 32, 40, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CF158[0], 0, 32;
- %load 32, V_$006CFA18[0];
- %load 33, V_$006CFA18[1];
- %load 34, V_$006CFA18[2];
- %load 35, V_$006CFA18[3];
- %load 36, V_$006CFA18[4];
- %load 37, V_$006CFA18[5];
- %load 38, V_$006CFA18[6];
- %load 39, V_$006CFA18[7];
- %load 40, V_$006CFCB8[0];
- %load 41, V_$006CFCB8[1];
- %load 42, V_$006CFCB8[2];
- %load 43, V_$006CFCB8[3];
- %load 44, V_$006CFCB8[4];
- %load 45, V_$006CFCB8[5];
- %load 46, V_$006CFCB8[6];
- %load 47, V_$006CFCB8[7];
- %or 32, 40, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CF750[0], 0, 32;
- %load 32, V_$006CD390[0];
- %load 33, V_$006CD390[1];
- %load 34, V_$006CD390[2];
- %load 35, V_$006CD390[3];
- %load 36, V_$006CD390[4];
- %load 37, V_$006CD390[5];
- %load 38, V_$006CD390[6];
- %load 39, V_$006CD390[7];
- %load 40, V_$006CDF58[0];
- %load 41, V_$006CDF58[1];
- %load 42, V_$006CDF58[2];
- %load 43, V_$006CDF58[3];
- %load 44, V_$006CDF58[4];
- %load 45, V_$006CDF58[5];
- %load 46, V_$006CDF58[6];
- %load 47, V_$006CDF58[7];
- %or 32, 40, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CD0D8[0], 0, 32;
- %jmp T_29;
- .thread T_29;
- .scope S_006CC9E8;
-T_30 ;
- %wait E_006CCA58;
- %load/v 32, V_$006CCC20[0], 5;
- %ix/load 0, 5;
- %assign/v0 V_$006CCD78[0], 0, 32;
- %load/v 32, V_$006D17B8[0], 1;
- %assign V_$006D0AC0[0], 0, 32;
- %load/v 32, V_$006D1678[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 32;
- %load/v 32, V_$006D14A8[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D0F08[0], 0, 32;
- %load/v 32, V_$006D1308[0], 1;
- %assign V_$006D04F0[0], 0, 32;
- %load/v 32, V_$006D0B40[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D01A8[0], 0, 32;
- %load/v 32, V_$006D1010[0], 1;
- %assign V_$006D0488[0], 0, 32;
- %load/v 32, V_$006D1360[0], 1;
- %assign V_$006D0E18[0], 0, 32;
- %load/v 32, V_$006CCC20[0], 5;
- %cmpi/u 32, 17, 5;
- %jmp/1 T_30.0, 6;
- %cmpi/u 32, 18, 5;
- %jmp/1 T_30.1, 6;
- %cmpi/u 32, 0, 5;
- %jmp/1 T_30.2, 6;
- %cmpi/u 32, 1, 5;
- %jmp/1 T_30.3, 6;
- %cmpi/u 32, 2, 5;
- %jmp/1 T_30.4, 6;
- %cmpi/u 32, 3, 5;
- %jmp/1 T_30.5, 6;
- %cmpi/u 32, 4, 5;
- %jmp/1 T_30.6, 6;
- %cmpi/u 32, 5, 5;
- %jmp/1 T_30.7, 6;
- %cmpi/u 32, 6, 5;
- %jmp/1 T_30.8, 6;
- %cmpi/u 32, 7, 5;
- %jmp/1 T_30.9, 6;
- %cmpi/u 32, 8, 5;
- %jmp/1 T_30.10, 6;
- %cmpi/u 32, 9, 5;
- %jmp/1 T_30.11, 6;
- %cmpi/u 32, 10, 5;
- %jmp/1 T_30.12, 6;
- %cmpi/u 32, 11, 5;
- %jmp/1 T_30.13, 6;
- %cmpi/u 32, 12, 5;
- %jmp/1 T_30.14, 6;
- %cmpi/u 32, 13, 5;
- %jmp/1 T_30.15, 6;
- %cmpi/u 32, 14, 5;
- %jmp/1 T_30.16, 6;
- %cmpi/u 32, 15, 5;
- %jmp/1 T_30.17, 6;
- %cmpi/u 32, 16, 5;
- %jmp/1 T_30.18, 6;
- %cmpi/u 32, 19, 5;
- %jmp/1 T_30.19, 6;
- %jmp T_30.20;
-T_30.0 ;
- %assign V_$006D0E18[0], 0, 1;
- %load/v 32, V_$006D1398[0], 1;
- %jmp/0xz T_30.21, 32;
- %ix/load 0, 4;
- %assign/v0 V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[4], 0, 0;
- %assign V_$006D0E18[0], 0, 0;
- %assign V_$006D0488[0], 0, 0;
-T_30.21 ;
- %jmp T_30.20;
-T_30.1 ;
- %assign V_$006D0E18[0], 0, 0;
- %assign V_$006D0AC0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 0;
- %assign V_$006D04F0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D01A8[0], 0, 0;
- %assign V_$006D0488[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D0F08[0], 0, 0;
- %assign V_$006CCD78[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[4], 0, 1;
- %jmp T_30.20;
-T_30.2 ;
- %assign V_$006D0AC0[0], 0, 0;
- %assign V_$006CCD78[0], 0, 0;
- %assign V_$006CCD78[1], 0, 1;
- %assign V_$006CCD78[2], 0, 0;
- %assign V_$006CCD78[3], 0, 1;
- %assign V_$006CCD78[4], 0, 0;
- %jmp T_30.20;
-T_30.3 ;
- %load 32, V_$006D1610[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_30.23, 4;
- %ix/load 0, 5;
- %assign/v0 V_$006CCD78[0], 0, 0;
- %load/v 32, V_$006CE7B0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 32;
- %assign V_$006D0AC0[0], 0, 1;
-T_30.23 ;
- %jmp T_30.20;
-T_30.4 ;
- %ix/load 0, 4;
- %assign/v0 V_$006CCD78[0], 0, 0;
- %assign V_$006CCD78[4], 0, 1;
- %jmp T_30.20;
-T_30.5 ;
- %assign V_$006D0AC0[0], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006CCD78[0], 0, 0;
- %assign V_$006CCD78[3], 0, 1;
- %assign V_$006CCD78[4], 0, 0;
- %jmp T_30.20;
-T_30.6 ;
- %assign V_$006D0AC0[0], 0, 0;
- %assign V_$006CCD78[0], 0, 1;
- %ix/load 0, 4;
- %assign/v0 V_$006CCD78[1], 0, 0;
- %jmp T_30.20;
-T_30.7 ;
- %assign V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[1], 0, 1;
- %assign V_$006CCD78[2], 0, 0;
- %assign V_$006CCD78[3], 0, 0;
- %assign V_$006CCD78[4], 0, 1;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 1;
- %assign V_$006D0AC0[0], 0, 1;
- %load/v 32, V_$006D14A8[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D0F08[0], 0, 32;
- %assign V_$006D04F0[0], 0, 1;
- %jmp T_30.20;
-T_30.8 ;
- %load 32, V_$006D12B0[0];
- %jmp/0xz T_30.25, 32;
- %ix/load 0, 3;
- %assign/v0 V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[3], 0, 0;
- %assign V_$006CCD78[4], 0, 0;
- %load 32, V_$006D1150[0];
- %load 33, V_$006D1150[1];
- %load 34, V_$006D1150[2];
- %load 35, V_$006D1150[3];
- %load 36, V_$006D1150[4];
- %load 37, V_$006D1150[5];
- %load 38, V_$006D1150[6];
- %load 39, V_$006D1150[7];
- %ix/load 0, 8;
- %assign/v0 V_$006D01A8[0], 0, 32;
-T_30.25 ;
- %jmp T_30.20;
-T_30.9 ;
- %load/v 32, V_$006D14A8[0], 10;
- %cmpi/u 32, 512, 10;
- %jmp/0xz T_30.27, 4;
- %assign V_$006CCD78[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[4], 0, 1;
- %assign V_$006D0488[0], 0, 1;
- %jmp T_30.28;
-T_30.27 ;
- %load/v 32, V_$006D0B40[7], 1;
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_30.29, 4;
- %assign V_$006CCD78[0], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[4], 0, 1;
- %jmp T_30.30;
-T_30.29 ;
- %assign V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[2], 0, 1;
- %assign V_$006CCD78[3], 0, 0;
- %assign V_$006CCD78[4], 0, 0;
-T_30.30 ;
-T_30.28 ;
- %jmp T_30.20;
-T_30.10 ;
- %load 32, V_$006D1610[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_30.31, 4;
- %assign V_$006CCD78[0], 0, 0;
- %assign V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[2], 0, 1;
- %assign V_$006CCD78[3], 0, 0;
- %assign V_$006CCD78[4], 0, 0;
- %load/v 32, V_$006CE188[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 32;
- %assign V_$006D0AC0[0], 0, 1;
-T_30.31 ;
- %jmp T_30.20;
-T_30.11 ;
- %assign V_$006D0AC0[0], 0, 0;
- %assign V_$006CCD78[0], 0, 0;
- %assign V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[2], 0, 1;
- %assign V_$006CCD78[3], 0, 1;
- %assign V_$006CCD78[4], 0, 0;
- %jmp T_30.20;
-T_30.12 ;
- %load 32, V_$006D1610[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_30.33, 4;
- %assign V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[2], 0, 0;
- %assign V_$006CCD78[3], 0, 1;
- %assign V_$006CCD78[4], 0, 0;
- %load/v 32, V_$006CF158[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 32;
- %assign V_$006D0AC0[0], 0, 1;
-T_30.33 ;
- %jmp T_30.20;
-T_30.13 ;
- %assign V_$006D0AC0[0], 0, 0;
- %assign V_$006CCD78[0], 0, 0;
- %ix/load 0, 3;
- %assign/v0 V_$006CCD78[1], 0, 1;
- %assign V_$006CCD78[4], 0, 0;
- %jmp T_30.20;
-T_30.14 ;
- %load 32, V_$006D1610[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_30.35, 4;
- %assign V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[1], 0, 1;
- %assign V_$006CCD78[2], 0, 0;
- %assign V_$006CCD78[3], 0, 1;
- %assign V_$006CCD78[4], 0, 0;
- %load/v 32, V_$006CF750[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 32;
- %assign V_$006D0AC0[0], 0, 1;
-T_30.35 ;
- %jmp T_30.20;
-T_30.15 ;
- %assign V_$006D0AC0[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D0F08[0], 0, 0;
- %load 32, V_$006D15B8[0];
- %jmp/0xz T_30.37, 32;
- %assign V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[2], 0, 1;
- %assign V_$006CCD78[3], 0, 0;
- %assign V_$006CCD78[4], 0, 0;
-T_30.37 ;
- %jmp T_30.20;
-T_30.16 ;
- %load 32, V_$006D1610[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_30.39, 4;
- %assign V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[1], 0, 0;
- %assign V_$006CCD78[2], 0, 1;
- %assign V_$006CCD78[3], 0, 1;
- %assign V_$006CCD78[4], 0, 0;
- %load/v 32, V_$006CD0D8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 32;
- %assign V_$006D0AC0[0], 0, 1;
-T_30.39 ;
- %jmp T_30.20;
-T_30.17 ;
- %load 32, V_$006D1610[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_30.41, 4;
- %assign V_$006CCD78[0], 0, 0;
- %assign V_$006CCD78[1], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006CCD78[2], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 1;
- %assign V_$006D0AC0[0], 0, 1;
-T_30.41 ;
- %jmp T_30.20;
-T_30.18 ;
- %assign V_$006D0AC0[0], 0, 0;
- %load 32, V_$006D1610[0];
- %cmpi/u 32, 0, 1;
- %jmp/0xz T_30.43, 4;
- %assign V_$006CCD78[0], 0, 1;
- %assign V_$006CCD78[1], 0, 1;
- %ix/load 0, 3;
- %assign/v0 V_$006CCD78[2], 0, 0;
- %load/v 32, V_$006CD788[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D07C0[0], 0, 32;
- %assign V_$006D0AC0[0], 0, 1;
-T_30.43 ;
- %jmp T_30.20;
-T_30.19 ;
- %assign V_$006CCD78[0], 0, 0;
- %assign V_$006CCD78[1], 0, 1;
- %assign V_$006CCD78[2], 0, 1;
- %assign V_$006CCD78[3], 0, 0;
- %assign V_$006CCD78[4], 0, 0;
- %assign V_$006D0AC0[0], 0, 0;
- %assign V_$006D04F0[0], 0, 0;
- %jmp T_30.20;
-T_30.20 ;
- %jmp T_30;
- .thread T_30, $push;
- .scope S_006CC9E8;
-T_31 ;
- %wait E_003DE478;
- %load 32, V_$006D1090[0];
- %jmp/0xz T_31.0, 32;
- %assign V_$006CCC20[0], 0, 0;
- %assign V_$006CCC20[1], 0, 1;
- %assign V_$006CCC20[2], 0, 0;
- %assign V_$006CCC20[3], 0, 0;
- %assign V_$006CCC20[4], 0, 1;
- %jmp T_31.1;
-T_31.0 ;
- %load/v 32, V_$006CCD78[0], 5;
- %ix/load 0, 5;
- %assign/v0 V_$006CCC20[0], 0, 32;
-T_31.1 ;
- %jmp T_31;
- .thread T_31;
- .scope S_006CC9E8;
-T_32 ;
- %wait E_003DE478;
- %load 32, V_$006D1090[0];
- %jmp/0xz T_32.0, 32;
- %assign V_$006D17B8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D1678[0], 0, 0;
- %assign V_$006D1308[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006D0B40[0], 0, 0;
- %assign V_$006D1010[0], 0, 0;
- %assign V_$006D1360[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006D14A8[0], 0, 0;
- %jmp T_32.1;
-T_32.0 ;
- %load/v 32, V_$006D0AC0[0], 1;
- %assign V_$006D17B8[0], 0, 32;
- %load/v 32, V_$006D07C0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D1678[0], 0, 32;
- %load/v 32, V_$006D04F0[0], 1;
- %assign V_$006D1308[0], 0, 32;
- %load/v 32, V_$006D01A8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006D0B40[0], 0, 32;
- %load/v 32, V_$006D0488[0], 1;
- %assign V_$006D1010[0], 0, 32;
- %load/v 32, V_$006D0E18[0], 1;
- %assign V_$006D1360[0], 0, 32;
- %load/v 32, V_$006D0F08[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006D14A8[0], 0, 32;
-T_32.1 ;
- %jmp T_32;
- .thread T_32;
- .scope S_006CABC8;
-T_33 ;
- %wait E_003DE478;
- %load 32, V_$006CBE80[0];
- %jmp/0xz T_33.0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006CC858[0], 0, 0;
- %assign V_$006CC7A8[0], 0, 0;
- %jmp T_33.1;
-T_33.0 ;
- %load 32, V_$006CBD38[0];
- %jmp/0xz T_33.2, 32;
- %load 32, V_$006CBA78[0];
- %load 33, V_$006CBA78[1];
- %load 34, V_$006CBA78[2];
- %load 35, V_$006CBA78[3];
- %load 36, V_$006CBA78[4];
- %load 37, V_$006CBA78[5];
- %load 38, V_$006CBA78[6];
- %load 39, V_$006CBA78[7];
- %ix/load 0, 8;
- %assign/v0 V_$006CC858[0], 0, 32;
- %assign V_$006CC7A8[0], 0, 1;
- %jmp T_33.3;
-T_33.2 ;
- %load 32, V_$006CBAB0[0];
- %jmp/0xz T_33.4, 32;
- %load 32, V_$006CC038[0];
- %load 33, V_$006CC038[1];
- %load 34, V_$006CC038[2];
- %load 35, V_$006CC038[3];
- %load 36, V_$006CC038[4];
- %load 37, V_$006CC038[5];
- %load 38, V_$006CC038[6];
- %load 39, V_$006CC038[7];
- %ix/load 0, 8;
- %assign/v0 V_$006CC858[0], 0, 32;
- %assign V_$006CC7A8[0], 0, 1;
- %jmp T_33.5;
-T_33.4 ;
- %load 32, V_$006CCE78[0];
- %jmp/0xz T_33.6, 32;
- %load 32, V_$006CC2F8[0];
- %load 33, V_$006CC2F8[1];
- %load 34, V_$006CC2F8[2];
- %load 35, V_$006CC2F8[3];
- %load 36, V_$006CC2F8[4];
- %load 37, V_$006CC2F8[5];
- %load 38, V_$006CC2F8[6];
- %load 39, V_$006CC2F8[7];
- %ix/load 0, 8;
- %assign/v0 V_$006CC858[0], 0, 32;
- %assign V_$006CC7A8[0], 0, 1;
- %jmp T_33.7;
-T_33.6 ;
- %load 32, V_$006CC720[0];
- %jmp/0xz T_33.8, 32;
- %load 32, V_$006CCF00[0];
- %load 33, V_$006CCF00[1];
- %load 34, V_$006CCF00[2];
- %load 35, V_$006CCF00[3];
- %load 36, V_$006CCF00[4];
- %load 37, V_$006CCF00[5];
- %load 38, V_$006CCF00[6];
- %load 39, V_$006CCF00[7];
- %ix/load 0, 8;
- %assign/v0 V_$006CC858[0], 0, 32;
- %assign V_$006CC7A8[0], 0, 1;
-T_33.8 ;
-T_33.7 ;
-T_33.5 ;
-T_33.3 ;
- %load 32, V_$006CC800[0];
- %jmp/0xz T_33.10, 32;
- %assign V_$006CC7A8[0], 0, 0;
-T_33.10 ;
-T_33.1 ;
- %jmp T_33;
- .thread T_33;
- .scope S_006CABC8;
-T_34 ;
- %wait E_003DE478;
- %load 32, V_$006CBE80[0];
- %jmp/0xz T_34.0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006CB750[0], 0, 0;
- %assign V_$006CB9B8[0], 0, 0;
- %jmp T_34.1;
-T_34.0 ;
- %load 32, V_$006CBEB8[0];
- %load 33, V_$006CBF60[0];
- %or 32, 33, 1;
- %load 33, V_$006CB4F8[0];
- %or 32, 33, 1;
- %load 33, V_$006CB568[0];
- %or 32, 33, 1;
- %jmp/0xz T_34.2, 32;
- %assign V_$006CB9B8[0], 0, 0;
-T_34.2 ;
- %load 32, V_$006CBA20[0];
- %jmp/0xz T_34.4, 32;
- %assign V_$006CB9B8[0], 0, 1;
- %load 32, V_$006CB5F0[0];
- %load 33, V_$006CB5F0[1];
- %load 34, V_$006CB5F0[2];
- %load 35, V_$006CB5F0[3];
- %load 36, V_$006CB5F0[4];
- %load 37, V_$006CB5F0[5];
- %load 38, V_$006CB5F0[6];
- %load 39, V_$006CB5F0[7];
- %ix/load 0, 8;
- %assign/v0 V_$006CB750[0], 0, 32;
-T_34.4 ;
-T_34.1 ;
- %jmp T_34;
- .thread T_34;
- .scope S_006C9128;
-T_35 ;
- %wait E_006C8530;
- %load/v 32, V_$006C9298[0], 2;
- %assign V_$006C92D0[0], 0, 32;
- %assign V_$006C92D0[1], 0, 33;
- %load/v 32, V_$006CA688[0], 1;
- %assign V_$006C9938[0], 0, 32;
- %load/v 32, V_$006CAB30[0], 1;
- %assign V_$006C99F8[0], 0, 32;
- %load/v 32, V_$006CB278[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CA2F0[0], 0, 32;
- %load/v 32, V_$006CA718[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C99C0[0], 0, 32;
- %load/v 32, V_$006C9BE0[0], 4;
- %ix/load 0, 4;
- %assign/v0 V_$006C9FA0[0], 0, 32;
- %load/v 32, V_$006C9D00[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C9440[0], 0, 32;
- %load/v 32, V_$006CAC78[0], 1;
- %assign V_$006CA268[0], 0, 32;
- %load/v 32, V_$006CAA28[0], 1;
- %assign V_$006CA118[0], 0, 32;
- %load/v 32, V_$006CAAD8[0], 1;
- %assign V_$006CA198[0], 0, 32;
- %load/v 32, V_$006C90B8[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C9660[0], 0, 32;
- %load/v 32, V_$006C9298[0], 2;
- %cmpi/u 32, 0, 2;
- %jmp/1 T_35.0, 6;
- %cmpi/u 32, 1, 2;
- %jmp/1 T_35.1, 6;
- %cmpi/u 32, 2, 2;
- %jmp/1 T_35.2, 6;
- %cmpi/u 32, 3, 2;
- %jmp/1 T_35.3, 6;
- %jmp T_35.4;
-T_35.0 ;
- %assign V_$006C9938[0], 0, 0;
- %assign V_$006C99F8[0], 0, 1;
- %load 32, V_$006CAB90[0];
- %jmp/0xz T_35.5, 32;
- %assign V_$006C92D0[0], 0, 1;
- %assign V_$006C92D0[1], 0, 0;
- %load 32, V_$006CAD08[0];
- %load 33, V_$006CAD08[1];
- %load 34, V_$006CAD08[2];
- %load 35, V_$006CAD08[3];
- %load 36, V_$006CAD08[4];
- %load 37, V_$006CAD08[5];
- %load 38, V_$006CAD08[6];
- %load 39, V_$006CAD08[7];
- %ix/load 0, 8;
- %assign/v0 V_$006CA2F0[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006C99C0[0], 0, 0;
- %ix/load 0, 4;
- %assign/v0 V_$006C9FA0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006C9440[0], 0, 0;
- %assign V_$006CA268[0], 0, 1;
- %assign V_$006C99F8[0], 0, 0;
-T_35.5 ;
- %jmp T_35.4;
-T_35.1 ;
- %load/v 32, V_$006C9D00[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C9440[0], 0, 32;
- %assign V_$006CA268[0], 0, 0;
- %assign V_$006C9938[0], 0, 0;
- %load/v 32, V_$006C9D00[0], 8;
- %load 40, V_$006C9CC8[0];
- %load 41, V_$006C9CC8[1];
- %load 42, V_$006C9CC8[2];
- %load 43, V_$006C9CC8[3];
- %load 44, V_$006C9CC8[4];
- %load 45, V_$006C9CC8[5];
- %load 46, V_$006C9CC8[6];
- %load 47, V_$006C9CC8[7];
- %cmp/u 32, 40, 8;
- %mov 32, 4, 1;
- %jmp/0xz T_35.7, 32;
- %assign V_$006C92D0[0], 0, 0;
- %assign V_$006C92D0[1], 0, 1;
- %assign V_$006CA118[0], 0, 0;
- %load/v 32, V_$006CB278[7], 1;
- %assign V_$006CA198[0], 0, 32;
- %mov 32, 0, 1;
- %load/v 33, V_$006CB278[0], 7;
- %ix/load 0, 8;
- %assign/v0 V_$006CA2F0[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006C9440[0], 0, 0;
-T_35.7 ;
- %jmp T_35.4;
-T_35.2 ;
- %load/v 32, V_$006C9D00[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C9440[0], 0, 32;
- %load/v 32, V_$006C9BE0[0], 4;
- %cmpi/u 32, 8, 4;
- %mov 32, 4, 1;
- %load 33, V_$006CAB90[0];
- %and 32, 33, 1;
- %jmp/0xz T_35.9, 32;
- %assign V_$006C92D0[0], 0, 1;
- %assign V_$006C92D0[1], 0, 0;
- %assign V_$006C9938[0], 0, 1;
- %load/v 32, V_$006CA718[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C9660[0], 0, 32;
- %load 32, V_$006CAD08[0];
- %load 33, V_$006CAD08[1];
- %load 34, V_$006CAD08[2];
- %load 35, V_$006CAD08[3];
- %load 36, V_$006CAD08[4];
- %load 37, V_$006CAD08[5];
- %load 38, V_$006CAD08[6];
- %load 39, V_$006CAD08[7];
- %ix/load 0, 8;
- %assign/v0 V_$006CA2F0[0], 0, 32;
- %ix/load 0, 4;
- %assign/v0 V_$006C9FA0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006C9440[0], 0, 0;
- %assign V_$006CA268[0], 0, 1;
- %jmp T_35.10;
-T_35.9 ;
- %load/v 32, V_$006C9BE0[0], 4;
- %cmpi/u 32, 8, 4;
- %jmp/0xz T_35.11, 4;
- %assign V_$006C92D0[0], 0, 0;
- %assign V_$006C92D0[1], 0, 0;
- %assign V_$006C9938[0], 0, 1;
- %load/v 32, V_$006CA718[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C9660[0], 0, 32;
- %jmp T_35.12;
-T_35.11 ;
- %load/v 32, V_$006C9D00[0], 8;
- %load 40, V_$006C9CC8[0];
- %load 41, V_$006C9CC8[1];
- %load 42, V_$006C9CC8[2];
- %load 43, V_$006C9CC8[3];
- %load 44, V_$006C9CC8[4];
- %load 45, V_$006C9CC8[5];
- %load 46, V_$006C9CC8[6];
- %load 47, V_$006C9CC8[7];
- %cmp/u 32, 40, 8;
- %mov 32, 4, 1;
- %jmp/0xz T_35.13, 32;
- %assign V_$006C92D0[0], 0, 1;
- %assign V_$006C92D0[1], 0, 0;
- %assign V_$006CA118[0], 0, 1;
- %load/v 32, V_$006C9BE0[0], 4;
- %addi 32, 1, 4;
- %ix/load 0, 4;
- %assign/v0 V_$006C9FA0[0], 0, 32;
- %ix/load 0, 8;
- %assign/v0 V_$006C9440[0], 0, 0;
- %load 32, V_$006CAA80[0];
- %load/v 33, V_$006CA718[0], 7;
- %ix/load 0, 8;
- %assign/v0 V_$006C99C0[0], 0, 32;
-T_35.13 ;
-T_35.12 ;
-T_35.10 ;
- %jmp T_35.4;
-T_35.3 ;
- %ix/load 0, 4;
- %assign/v0 V_$006C9FA0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006C9440[0], 0, 0;
- %assign V_$006CA268[0], 0, 0;
- %assign V_$006C9938[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006CA2F0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006C99C0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006C9660[0], 0, 0;
- %assign V_$006CA198[0], 0, 0;
- %assign V_$006CA118[0], 0, 0;
- %assign V_$006C99F8[0], 0, 0;
- %assign V_$006C92D0[0], 0, 0;
- %assign V_$006C92D0[1], 0, 0;
- %jmp T_35.4;
-T_35.4 ;
- %jmp T_35;
- .thread T_35, $push;
- .scope S_006C9128;
-T_36 ;
- %wait E_003DE478;
- %load 32, V_$006CAEC0[0];
- %jmp/0xz T_36.0, 32;
- %assign V_$006C9298[0], 0, 1;
- %assign V_$006C9298[1], 0, 1;
- %jmp T_36.1;
-T_36.0 ;
- %load/v 32, V_$006C92D0[0], 2;
- %assign V_$006C9298[0], 0, 32;
- %assign V_$006C9298[1], 0, 33;
-T_36.1 ;
- %jmp T_36;
- .thread T_36;
- .scope S_006C9128;
-T_37 ;
- %wait E_003DE478;
- %load 32, V_$006CAEC0[0];
- %jmp/0xz T_37.0, 32;
- %assign V_$006CA688[0], 0, 0;
- %assign V_$006CAB30[0], 0, 0;
- %assign V_$006CAC78[0], 0, 0;
- %assign V_$006CAA28[0], 0, 0;
- %assign V_$006CAAD8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006C90B8[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006CB278[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006CA718[0], 0, 0;
- %ix/load 0, 4;
- %assign/v0 V_$006C9BE0[0], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006C9D00[0], 0, 0;
- %jmp T_37.1;
-T_37.0 ;
- %load/v 32, V_$006C9938[0], 1;
- %assign V_$006CA688[0], 0, 32;
- %load/v 32, V_$006C99F8[0], 1;
- %assign V_$006CAB30[0], 0, 32;
- %load/v 32, V_$006CA268[0], 1;
- %assign V_$006CAC78[0], 0, 32;
- %load/v 32, V_$006CA118[0], 1;
- %assign V_$006CAA28[0], 0, 32;
- %load/v 32, V_$006CA198[0], 1;
- %assign V_$006CAAD8[0], 0, 32;
- %load/v 32, V_$006C9660[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C90B8[0], 0, 32;
- %load/v 32, V_$006CA2F0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CB278[0], 0, 32;
- %load/v 32, V_$006C99C0[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006CA718[0], 0, 32;
- %load/v 32, V_$006C9FA0[0], 4;
- %ix/load 0, 4;
- %assign/v0 V_$006C9BE0[0], 0, 32;
- %load/v 32, V_$006C9440[0], 8;
- %ix/load 0, 8;
- %assign/v0 V_$006C9D00[0], 0, 32;
-T_37.1 ;
- %jmp T_37;
- .thread T_37;
- .scope S_006C5C68;
-T_38 ;
- %wait E_003DE478;
- %load 32, V_$006C6048[0];
- %load 33, V_$006C6048[1];
- %load 34, V_$006C6048[2];
- %load 35, V_$006C6048[3];
- %load 36, V_$006C6048[4];
- %load 37, V_$006C6048[5];
- %load 38, V_$006C6048[6];
- %load 39, V_$006C6048[7];
- %load 40, V_$006C6048[8];
- %ix/get 3, 32, 9;
- %ix/mul 3, 8;
- %load/m 32, M_$006C68E0;
- %ix/add 3, 1;
- %load/m 33, M_$006C68E0;
- %ix/add 3, 1;
- %load/m 34, M_$006C68E0;
- %ix/add 3, 1;
- %load/m 35, M_$006C68E0;
- %ix/add 3, 1;
- %load/m 36, M_$006C68E0;
- %ix/add 3, 1;
- %load/m 37, M_$006C68E0;
- %ix/add 3, 1;
- %load/m 38, M_$006C68E0;
- %ix/add 3, 1;
- %load/m 39, M_$006C68E0;
- %ix/load 0, 8;
- %assign/v0 V_$006C53E0[0], 0, 32;
- %jmp T_38;
- .thread T_38;
- .scope S_006C5C68;
-T_39 ;
- %wait E_003DE0F8;
- %load 32, V_$006C5300[0];
- %jmp/0xz T_39.0, 32;
- %load 32, V_$006C6340[0];
- %load 33, V_$006C6340[1];
- %load 34, V_$006C6340[2];
- %load 35, V_$006C6340[3];
- %load 36, V_$006C6340[4];
- %load 37, V_$006C6340[5];
- %load 38, V_$006C6340[6];
- %load 39, V_$006C6340[7];
- %load 40, V_$006C5B38[0];
- %load 41, V_$006C5B38[1];
- %load 42, V_$006C5B38[2];
- %load 43, V_$006C5B38[3];
- %load 44, V_$006C5B38[4];
- %load 45, V_$006C5B38[5];
- %load 46, V_$006C5B38[6];
- %load 47, V_$006C5B38[7];
- %load 48, V_$006C5B38[8];
- %ix/get 3, 40, 9;
- %ix/mul 3, 8;
- %jmp/1 t_833, 4;
- %assign/m M_$006C68E0, 0, 32;
- %ix/add 3, 1;
- %assign/m M_$006C68E0, 0, 33;
- %ix/add 3, 1;
- %assign/m M_$006C68E0, 0, 34;
- %ix/add 3, 1;
- %assign/m M_$006C68E0, 0, 35;
- %ix/add 3, 1;
- %assign/m M_$006C68E0, 0, 36;
- %ix/add 3, 1;
- %assign/m M_$006C68E0, 0, 37;
- %ix/add 3, 1;
- %assign/m M_$006C68E0, 0, 38;
- %ix/add 3, 1;
- %assign/m M_$006C68E0, 0, 39;
-t_833 ;
-T_39.0 ;
- %jmp T_39;
- .thread T_39;
- .scope S_006C5A78;
-T_40 ;
- %wait E_003DE0F8;
- %load/v 32, V_$006C73C8[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C7F50[0], 0, 32;
- %load 32, V_$006C8618[0];
- %load 33, V_$006C8210[0];
- %or 32, 33, 1;
- %jmp/0xz T_40.0, 32;
- %assign V_$006C8098[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006C5290[0], 0, 0;
- %jmp T_40.1;
-T_40.0 ;
- %load 32, V_$006C81A0[0];
- %jmp/0xz T_40.2, 32;
- %load/v 32, V_$006C5290[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C5290[0], 0, 32;
-T_40.2 ;
- %load/v 32, V_$006C7F50[0], 9;
- %load/v 41, V_$006C5290[0], 9;
- %cmp/u 32, 41, 9;
- %mov 32, 4, 1;
- %load/v 33, V_$006C7F50[9], 1;
- %load/v 34, V_$006C5290[9], 1;
- %cmp/u 33, 34, 1;
- %inv 4, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_40.4, 32;
- %assign V_$006C8098[0], 0, 1;
- %jmp T_40.5;
-T_40.4 ;
- %assign V_$006C8098[0], 0, 0;
-T_40.5 ;
-T_40.1 ;
- %jmp T_40;
- .thread T_40;
- .scope S_006C5A78;
-T_41 ;
- %wait E_003DDD60;
- %load/v 32, V_$006C5258[0], 10;
- %load/v 42, V_$006C73C8[0], 10;
- %sub 32, 42, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C52C8[0], 0, 32;
- %jmp T_41;
- .thread T_41, $push;
- .scope S_006C5A78;
-T_42 ;
- %wait E_003DE478;
- %load/v 32, V_$006C52C8[0], 10;
- %mov 42, 0, 8;
- %ix/load 0, 16;
- %assign/v0 V_$006C82B8[0], 0, 32;
- %load/v 32, V_$006C5290[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C5258[0], 0, 32;
- %load 32, V_$006C85E0[0];
- %load 33, V_$006C81D8[0];
- %or 32, 33, 1;
- %jmp/0xz T_42.0, 32;
- %assign V_$006C7FF8[0], 0, 1;
- %ix/load 0, 10;
- %assign/v0 V_$006C73C8[0], 0, 0;
- %assign V_$006C8030[0], 0, 0;
- %jmp T_42.1;
-T_42.0 ;
- %load 32, V_$006C8118[0];
- %assign V_$006C8030[0], 0, 32;
- %load/v 33, V_$006C8030[0], 1;
- %cmpi/u 33, 0, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_42.2, 32;
- %load 32, V_$006C7978[0];
- %load 33, V_$006C7978[1];
- %load 34, V_$006C7978[2];
- %load 35, V_$006C7978[3];
- %load 36, V_$006C7978[4];
- %load 37, V_$006C7978[5];
- %load 38, V_$006C7978[6];
- %load 39, V_$006C7978[7];
- %ix/load 0, 8;
- %assign/v0 V_$006C7CF0[0], 0, 32;
- %load/v 32, V_$006C73C8[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C73C8[0], 0, 32;
-T_42.2 ;
- %load/v 32, V_$006C5258[0], 10;
- %load/v 42, V_$006C73C8[0], 10;
- %cmp/u 32, 42, 10;
- %mov 32, 4, 1;
- %jmp/0xz T_42.4, 32;
- %assign V_$006C7FF8[0], 0, 1;
- %jmp T_42.5;
-T_42.4 ;
- %assign V_$006C7FF8[0], 0, 0;
-T_42.5 ;
-T_42.1 ;
- %jmp T_42;
- .thread T_42;
- .scope S_006C5A78;
-T_43 ;
- %wait E_005F17F0;
- %load/v 32, V_$006C5290[0], 9;
- %ix/load 0, 9;
- %assign/v0 V_$006C7270[0], 0, 32;
- %load/v 32, V_$006C73C8[0], 9;
- %ix/load 0, 9;
- %assign/v0 V_$006C77D8[0], 0, 32;
- %jmp T_43;
- .thread T_43, $push;
- .scope S_006C5098;
-T_44 ;
- %wait E_003DE0F8;
- %load 32, V_$006C5A08[0];
- %load 33, V_$006C5478[0];
- %and 32, 33, 1;
- %load 33, V_$006C5060[0];
- %load 34, V_$006C5060[1];
- %load 35, V_$006C5060[2];
- %cmpi/u 33, 4, 3;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %load 33, V_$006C4F40[0];
- %and 32, 33, 1;
- %load 33, V_$006C51F8[0];
- %and 32, 33, 1;
- %jmp/0xz T_44.0, 32;
- %assign V_$006C54E8[0], 0, 1;
- %jmp T_44.1;
-T_44.0 ;
- %assign V_$006C54E8[0], 0, 0;
-T_44.1 ;
- %jmp T_44;
- .thread T_44;
- .scope S_006C5098;
-T_45 ;
- %wait E_003DE0F8;
- %load 32, V_$006C58F0[0];
- %jmp/0xz T_45.0, 32;
- %ix/load 0, 6;
- %assign/v0 V_$006C5548[0], 0, 0;
- %jmp T_45.1;
-T_45.0 ;
- %load/v 32, V_$006C54E8[0], 1;
- %jmp/0xz T_45.2, 32;
- %ix/load 0, 6;
- %assign/v0 V_$006C5548[0], 0, 1;
- %jmp T_45.3;
-T_45.2 ;
- %load/v 32, V_$006C5548[1], 5;
- %mov 37, 0, 1;
- %ix/load 0, 6;
- %assign/v0 V_$006C5548[0], 0, 32;
-T_45.3 ;
-T_45.1 ;
- %jmp T_45;
- .thread T_45;
- .scope S_006C5098;
-T_46 ;
- %wait E_003DE478;
- %load 32, V_$006C5580[0];
- %assign V_$006C55F0[0], 0, 32;
- %load/v 32, V_$006C55F0[0], 1;
- %assign V_$006C55B8[0], 0, 32;
- %jmp T_46;
- .thread T_46;
- .scope S_006C5098;
-T_47 ;
- %wait E_006C45B0;
- %load 32, V_$006C5060[0];
- %load 33, V_$006C5060[1];
- %load 34, V_$006C5060[2];
- %cmpi/u 32, 0, 3;
- %mov 32, 4, 1;
- %load 33, V_$006C5A08[0];
- %and 32, 33, 1;
- %load 33, V_$006C4F40[0];
- %and 32, 33, 1;
- %load 33, V_$006C5478[0];
- %and 32, 33, 1;
- %jmp/0xz T_47.0, 32;
- %assign V_$006C54B0[0], 0, 1;
- %jmp T_47.1;
-T_47.0 ;
- %assign V_$006C54B0[0], 0, 0;
-T_47.1 ;
- %jmp T_47;
- .thread T_47, $push;
- .scope S_006C2228;
-T_48 ;
- %wait E_003DE0F8;
- %load 32, V_$006AC4E0[0];
- %load 33, V_$006AC4E0[1];
- %load 34, V_$006AC4E0[2];
- %load 35, V_$006AC4E0[3];
- %load 36, V_$006AC4E0[4];
- %load 37, V_$006AC4E0[5];
- %load 38, V_$006AC4E0[6];
- %load 39, V_$006AC4E0[7];
- %load 40, V_$006AC4E0[8];
- %ix/get 3, 32, 9;
- %ix/mul 3, 8;
- %load/m 32, M_$005D1E00;
- %ix/add 3, 1;
- %load/m 33, M_$005D1E00;
- %ix/add 3, 1;
- %load/m 34, M_$005D1E00;
- %ix/add 3, 1;
- %load/m 35, M_$005D1E00;
- %ix/add 3, 1;
- %load/m 36, M_$005D1E00;
- %ix/add 3, 1;
- %load/m 37, M_$005D1E00;
- %ix/add 3, 1;
- %load/m 38, M_$005D1E00;
- %ix/add 3, 1;
- %load/m 39, M_$005D1E00;
- %ix/load 0, 8;
- %assign/v0 V_$00639738[0], 0, 32;
- %jmp T_48;
- .thread T_48;
- .scope S_006C2228;
-T_49 ;
- %wait E_003DE478;
- %load 32, V_$006C27D8[0];
- %jmp/0xz T_49.0, 32;
- %load 32, V_$006AD2C8[0];
- %load 33, V_$006AD2C8[1];
- %load 34, V_$006AD2C8[2];
- %load 35, V_$006AD2C8[3];
- %load 36, V_$006AD2C8[4];
- %load 37, V_$006AD2C8[5];
- %load 38, V_$006AD2C8[6];
- %load 39, V_$006AD2C8[7];
- %load 40, V_$006AC480[0];
- %load 41, V_$006AC480[1];
- %load 42, V_$006AC480[2];
- %load 43, V_$006AC480[3];
- %load 44, V_$006AC480[4];
- %load 45, V_$006AC480[5];
- %load 46, V_$006AC480[6];
- %load 47, V_$006AC480[7];
- %load 48, V_$006AC480[8];
- %ix/get 3, 40, 9;
- %ix/mul 3, 8;
- %jmp/1 t_863, 4;
- %assign/m M_$005D1E00, 0, 32;
- %ix/add 3, 1;
- %assign/m M_$005D1E00, 0, 33;
- %ix/add 3, 1;
- %assign/m M_$005D1E00, 0, 34;
- %ix/add 3, 1;
- %assign/m M_$005D1E00, 0, 35;
- %ix/add 3, 1;
- %assign/m M_$005D1E00, 0, 36;
- %ix/add 3, 1;
- %assign/m M_$005D1E00, 0, 37;
- %ix/add 3, 1;
- %assign/m M_$005D1E00, 0, 38;
- %ix/add 3, 1;
- %assign/m M_$005D1E00, 0, 39;
-t_863 ;
-T_49.0 ;
- %jmp T_49;
- .thread T_49;
- .scope S_006C2110;
-T_50 ;
- %wait E_003DE478;
- %load/v 32, V_$006C3600[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C3D38[0], 0, 32;
- %load 32, V_$006C46F0[0];
- %load 33, V_$006C4360[0];
- %or 32, 33, 1;
- %jmp/0xz T_50.0, 32;
- %assign V_$006C4260[0], 0, 0;
- %ix/load 0, 10;
- %assign/v0 V_$006C2B10[0], 0, 0;
- %jmp T_50.1;
-T_50.0 ;
- %load 32, V_$006C42D0[0];
- %jmp/0xz T_50.2, 32;
- %load/v 32, V_$006C2B10[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C2B10[0], 0, 32;
-T_50.2 ;
- %load/v 32, V_$006C3D38[0], 9;
- %load/v 41, V_$006C2B10[0], 9;
- %cmp/u 32, 41, 9;
- %mov 32, 4, 1;
- %load/v 33, V_$006C3D38[9], 1;
- %load/v 34, V_$006C2B10[9], 1;
- %cmp/u 33, 34, 1;
- %inv 4, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_50.4, 32;
- %assign V_$006C4260[0], 0, 1;
- %jmp T_50.5;
-T_50.4 ;
- %assign V_$006C4260[0], 0, 0;
-T_50.5 ;
-T_50.1 ;
- %jmp T_50;
- .thread T_50;
- .scope S_006C2110;
-T_51 ;
- %wait E_005EE048;
- %load/v 32, V_$006C3170[0], 10;
- %load/v 42, V_$006C3600[0], 10;
- %sub 32, 42, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C2810[0], 0, 32;
- %jmp T_51;
- .thread T_51, $push;
- .scope S_006C2110;
-T_52 ;
- %wait E_003DE0F8;
- %load/v 32, V_$006C2810[0], 10;
- %mov 42, 0, 8;
- %ix/load 0, 16;
- %assign/v0 V_$006C4398[0], 0, 32;
- %load/v 32, V_$006C2B10[0], 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C3170[0], 0, 32;
- %load 32, V_$006C4698[0];
- %load 33, V_$006C4308[0];
- %or 32, 33, 1;
- %jmp/0xz T_52.0, 32;
- %assign V_$006C41F0[0], 0, 1;
- %ix/load 0, 10;
- %assign/v0 V_$006C3600[0], 0, 0;
- %assign V_$006C4228[0], 0, 0;
- %jmp T_52.1;
-T_52.0 ;
- %load 32, V_$006C4298[0];
- %assign V_$006C4228[0], 0, 32;
- %load/v 33, V_$006C4228[0], 1;
- %cmpi/u 33, 0, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %jmp/0xz T_52.2, 32;
- %load 32, V_$006C3898[0];
- %load 33, V_$006C3898[1];
- %load 34, V_$006C3898[2];
- %load 35, V_$006C3898[3];
- %load 36, V_$006C3898[4];
- %load 37, V_$006C3898[5];
- %load 38, V_$006C3898[6];
- %load 39, V_$006C3898[7];
- %ix/load 0, 8;
- %assign/v0 V_$006C4090[0], 0, 32;
- %load/v 32, V_$006C3600[0], 10;
- %addi 32, 1, 10;
- %ix/load 0, 10;
- %assign/v0 V_$006C3600[0], 0, 32;
-T_52.2 ;
- %load/v 32, V_$006C3170[0], 10;
- %load/v 42, V_$006C3600[0], 10;
- %cmp/u 32, 42, 10;
- %mov 32, 4, 1;
- %jmp/0xz T_52.4, 32;
- %assign V_$006C41F0[0], 0, 1;
- %jmp T_52.5;
-T_52.4 ;
- %assign V_$006C41F0[0], 0, 0;
-T_52.5 ;
-T_52.1 ;
- %jmp T_52;
- .thread T_52;
- .scope S_006C2110;
-T_53 ;
- %wait E_005EEF18;
- %load/v 32, V_$006C2B10[0], 9;
- %ix/load 0, 9;
- %assign/v0 V_$006C3508[0], 0, 32;
- %load/v 32, V_$006C3600[0], 9;
- %ix/load 0, 9;
- %assign/v0 V_$006C3740[0], 0, 32;
- %jmp T_53;
- .thread T_53, $push;
- .scope S_006C1658;
-T_54 ;
- %wait E_003DE0F8;
- %load 32, V_$006685B0[0];
- %load 33, V_$006A7BA8[0];
- %and 32, 33, 1;
- %load 33, V_$006A4EE8[0];
- %load 34, V_$006A4EE8[1];
- %load 35, V_$006A4EE8[2];
- %cmpi/u 33, 4, 3;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %load 33, V_$006AA8A8[0];
- %and 32, 33, 1;
- %load 33, V_$0065A890[0];
- %and 32, 33, 1;
- %jmp/0xz T_54.0, 32;
- %assign V_$006A7DD8[0], 0, 1;
- %jmp T_54.1;
-T_54.0 ;
- %assign V_$006A7DD8[0], 0, 0;
-T_54.1 ;
- %jmp T_54;
- .thread T_54;
- .scope S_006C1658;
-T_55 ;
- %wait E_003DE0F8;
- %load 32, V_$0065D6E8[0];
- %jmp/0xz T_55.0, 32;
- %ix/load 0, 6;
- %assign/v0 V_$00666B38[0], 0, 0;
- %jmp T_55.1;
-T_55.0 ;
- %load/v 32, V_$006A7DD8[0], 1;
- %jmp/0xz T_55.2, 32;
- %ix/load 0, 6;
- %assign/v0 V_$00666B38[0], 0, 1;
- %jmp T_55.3;
-T_55.2 ;
- %load/v 32, V_$00666B38[1], 5;
- %mov 37, 0, 1;
- %ix/load 0, 6;
- %assign/v0 V_$00666B38[0], 0, 32;
-T_55.3 ;
-T_55.1 ;
- %jmp T_55;
- .thread T_55;
- .scope S_006C1658;
-T_56 ;
- %wait E_003DE478;
- %load 32, V_$006A8D90[0];
- %assign V_$006A8850[0], 0, 32;
- %load/v 32, V_$006A8850[0], 1;
- %assign V_$006A9EA0[0], 0, 32;
- %jmp T_56;
- .thread T_56;
- .scope S_006C1658;
-T_57 ;
- %wait E_003DDC30;
- %load 32, V_$006A4EE8[0];
- %load 33, V_$006A4EE8[1];
- %load 34, V_$006A4EE8[2];
- %cmpi/u 32, 0, 3;
- %jmp/1 T_57.0, 6;
- %cmpi/u 32, 2, 3;
- %jmp/1 T_57.1, 6;
- %cmpi/u 32, 3, 3;
- %jmp/1 T_57.2, 6;
- %ix/load 0, 8;
- %assign/v0 V_$006A5290[0], 0, 0;
- %jmp T_57.4;
-T_57.0 ;
- %load 32, V_$00660078[0];
- %load 33, V_$00660078[1];
- %load 34, V_$00660078[2];
- %load 35, V_$00660078[3];
- %load 36, V_$00660078[4];
- %load 37, V_$00660078[5];
- %load 38, V_$00660078[6];
- %load 39, V_$00660078[7];
- %ix/load 0, 8;
- %assign/v0 V_$006A5290[0], 0, 32;
- %jmp T_57.4;
-T_57.1 ;
- %load 32, V_$00666678[8];
- %load 33, V_$00666678[9];
- %load 34, V_$00666678[10];
- %load 35, V_$00666678[11];
- %load 36, V_$00666678[12];
- %load 37, V_$00666678[13];
- %load 38, V_$00666678[14];
- %load 39, V_$00666678[15];
- %ix/load 0, 8;
- %assign/v0 V_$006A5290[0], 0, 32;
- %jmp T_57.4;
-T_57.2 ;
- %load 32, V_$00666678[0];
- %load 33, V_$00666678[1];
- %load 34, V_$00666678[2];
- %load 35, V_$00666678[3];
- %load 36, V_$00666678[4];
- %load 37, V_$00666678[5];
- %load 38, V_$00666678[6];
- %load 39, V_$00666678[7];
- %ix/load 0, 8;
- %assign/v0 V_$006A5290[0], 0, 32;
- %jmp T_57.4;
-T_57.4 ;
- %jmp T_57;
- .thread T_57, $push;
- .scope S_006C1658;
-T_58 ;
- %wait E_003DDB00;
- %load 32, V_$006A4EE8[0];
- %load 33, V_$006A4EE8[1];
- %load 34, V_$006A4EE8[2];
- %cmpi/u 32, 0, 3;
- %mov 32, 4, 1;
- %load 33, V_$006685B0[0];
- %cmpi/u 33, 0, 1;
- %mov 33, 4, 1;
- %and 32, 33, 1;
- %load 33, V_$006AA8A8[0];
- %and 32, 33, 1;
- %load 33, V_$006A7BA8[0];
- %and 32, 33, 1;
- %jmp/0xz T_58.0, 32;
- %assign V_$006A76F0[0], 0, 1;
- %jmp T_58.1;
-T_58.0 ;
- %assign V_$006A76F0[0], 0, 0;
-T_58.1 ;
- %jmp T_58;
- .thread T_58, $push;
- .scope S_00624D88;
-T_59 ;
- %set/v V_$0068AE60[0], 2, 8;
- %set/v V_$0069AA18[0], 2, 8;
- %set V_$0069A858[0], 0;
- %set V_$006607B0[0], 2;
- %set V_$006A5C98[0], 2;
- %set V_$006A4238[0], 2;
- %delay 1000;
- %end;
- .thread T_59;
- .scope S_00633880;
-T_60 ;
- %set/v V_$006B08C8[0], 0, 2;
- %end;
- .thread T_60;
- .scope S_00633880;
-T_61 ;
- %load/v 32, V_$006B08C8[0], 2;
- %cmpi/u 32, 0, 2;
- %jmp/1 T_61.0, 6;
- %cmpi/u 32, 1, 2;
- %jmp/1 T_61.1, 6;
- %cmpi/u 32, 2, 2;
- %jmp/1 T_61.2, 6;
- %jmp T_61.3;
-T_61.0 ;
- %set/v V_$006B01E8[0], 1, 8;
- %fork TD_testHarness.u_sdModel.txRxByte, S_006399E8;
- %join;
- %load/v 32, V_$006B00C0[0], 8;
- %set/v V_$006B0718[0], 32, 8;
- %load/v 32, V_$006B0718[0], 8;
- %cmpi/u 32, 255, 8;
- %jmp/0xz T_61.4, 4;
- %assign V_$006B08C8[0], 0, 1;
- %assign V_$006B08C8[1], 0, 0;
- %ix/load 0, 8;
- %assign/v0 V_$006B0438[0], 0, 0;
-T_61.4 ;
- %jmp T_61.3;
-T_61.1 ;
- %set/v V_$006B01E8[0], 1, 8;
- %fork TD_testHarness.u_sdModel.txRxByte, S_006399E8;
- %join;
- %load/v 32, V_$006B00C0[0], 8;
- %set/v V_$006B0718[0], 32, 8;
- %load/v 32, V_$006B0718[0], 8;
- %cmpi/u 32, 255, 8;
- %jmp/0xz T_61.6, 4;
- %load/v 32, V_$006B0438[0], 8;
- %addi 32, 1, 8;
- %ix/load 0, 8;
- %assign/v0 V_$006B0438[0], 0, 32;
- %load/v 32, V_$006B0438[0], 8;
- %cmpi/u 32, 10, 8;
- %jmp/0xz T_61.8, 4;
- %load/v 32, V_$006B0578[0], 8;
- %set/v V_$006B01E8[0], 32, 8;
- %fork TD_testHarness.u_sdModel.txRxByte, S_006399E8;
- %join;
- %load/v 32, V_$006B00C0[0], 8;
- %set/v V_$006B0718[0], 32, 8;
- %assign V_$006B08C8[0], 0, 0;
- %assign V_$006B08C8[1], 0, 1;
-T_61.8 ;
- %jmp T_61.7;
-T_61.6 ;
- %assign V_$006B08C8[0], 0, 0;
- %assign V_$006B08C8[1], 0, 0;
-T_61.7 ;
- %jmp T_61.3;
-T_61.2 ;
- %set/v V_$006B01E8[0], 1, 8;
- %fork TD_testHarness.u_sdModel.txRxByte, S_006399E8;
- %join;
- %load/v 32, V_$006B00C0[0], 8;
- %set/v V_$006B0718[0], 32, 8;
- %load/v 32, V_$006B0718[0], 8;
- %cmpi/u 32, 255, 8;
- %inv 4, 1;
- %jmp/0xz T_61.10, 4;
- %assign V_$006B08C8[0], 0, 0;
- %assign V_$006B08C8[1], 0, 0;
-T_61.10 ;
- %jmp T_61.3;
-T_61.3 ;
- %jmp T_61;
- .thread T_61;
- .scope S_006338F0;
-T_62 ;
- %vpi_call "$dumpfile", "wave.vcd";
- %vpi_call "$dumpvars", 1'sb0, S_006C1500;
- %end;
- .thread T_62;
- .scope S_006338F0;
-T_63 ;
- %wait E_003DE0F8;
- %wait E_003DE0F8;
- %wait E_003DE0F8;
- %wait E_003DE0F8;
- %wait E_003DE0F8;
- %wait E_003DE0F8;
- %wait E_003DE0F8;
- %wait E_003DE0F8;
- %assign V_$006E0BD0[0], 0, 1;
- %wait E_003DE0F8;
- %assign V_$006E0BD0[0], 0, 0;
- %wait E_003DE0F8;
- %end;
- .thread T_63;
- .scope S_006338F0;
-T_64 ;
- %delay 20000;
- %assign V_$006DF4B8[0], 0, 0;
- %delay 20000;
- %assign V_$006DF4B8[0], 0, 1;
- %jmp T_64;
- .thread T_64;
- .scope S_006338F0;
-T_65 ;
- %delay 10000;
- %assign V_$006E3508[0], 0, 0;
- %delay 10000;
- %assign V_$006E3508[0], 0, 1;
- %jmp T_65;
- .thread T_65;
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