Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5

7 files changed, 275 insertions, 0 deletions

diff --git a/opencores/ethernet_tri_mode/syn/CVS/Entries b/opencores/ethernet_tri_mode/syn/CVS/Entries
new file mode 100644
index 000000000..b6b97bde6
--- /dev/null
+++ b/opencores/ethernet_tri_mode/syn/CVS/Entries
@@ -0,0 +1,4 @@
+/syn.prj/1.2/Thu Jan 19 14:07:57 2006//
+/syn_altrea.prj/1.1/Sun Jun 25 05:09:02 2006//
+/syn_xilinx.prj/1.1/Sun Jun 25 05:09:02 2006//
+D
diff --git a/opencores/ethernet_tri_mode/syn/CVS/Repository b/opencores/ethernet_tri_mode/syn/CVS/Repository
new file mode 100644
index 000000000..300767cae
--- /dev/null
+++ b/opencores/ethernet_tri_mode/syn/CVS/Repository
@@ -0,0 +1 @@
+ethernet_tri_mode/syn
diff --git a/opencores/ethernet_tri_mode/syn/CVS/Root b/opencores/ethernet_tri_mode/syn/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/opencores/ethernet_tri_mode/syn/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/opencores/ethernet_tri_mode/syn/CVS/Template b/opencores/ethernet_tri_mode/syn/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/opencores/ethernet_tri_mode/syn/CVS/Template
diff --git a/opencores/ethernet_tri_mode/syn/syn.prj b/opencores/ethernet_tri_mode/syn/syn.prj
new file mode 100644
index 000000000..568a7a4ed
--- /dev/null
+++ b/opencores/ethernet_tri_mode/syn/syn.prj
@@ -0,0 +1,86 @@
+#-- Synplicity, Inc.
+#-- Version Synplify 8.1
+#-- Project file D:\root\home\ethernet_tri_mode\syn\syn.prj
+#-- Written on Thu Jan 19 20:25:55 2006
+
+
+#add_file options
+add_file -verilog "../rtl/verilog/header.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"
+add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v"
+add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v"
+add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v"
+add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v"
+add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v"
+add_file -verilog "../rtl/verilog/TECH/duram.v"
+add_file -verilog "../rtl/verilog/RMON.v"
+add_file -verilog "../rtl/verilog/MAC_rx.v"
+add_file -verilog "../rtl/verilog/MAC_tx.v"
+add_file -verilog "../rtl/verilog/miim/eth_clockgen.v"
+add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v"
+add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v"
+add_file -verilog "../rtl/verilog/miim/timescale.v"
+add_file -verilog "../rtl/verilog/TECH/CLK_SWITCH.v"
+add_file -verilog "../rtl/verilog/TECH/CLK_DIV2.v"
+add_file -verilog "../rtl/verilog/eth_miim.v"
+add_file -verilog "../rtl/verilog/Clk_ctrl.v"
+add_file -verilog "../rtl/verilog/Phy_int.v"
+add_file -verilog "../rtl/verilog/Reg_int.v"
+add_file -verilog "../rtl/verilog/MAC_top.v"
+
+
+#implementation: "syn"
+impl -add syn
+
+#device options
+set_option -technology STRATIX
+set_option -part EP1S10
+set_option -package FC780
+set_option -speed_grade -5
+
+#compilation/mapping options
+set_option -default_enum_encoding onehot
+set_option -symbolic_fsm_compiler 0
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+
+#map options
+set_option -frequency auto
+set_option -run_prop_extract 0
+set_option -fanout_limit 500
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -retiming 0
+set_option -verification_mode 0
+set_option -fixgatedclocks 0
+set_option -no_sequential_opt 0
+
+#simulation options
+set_option -write_verilog 1
+set_option -write_vhdl 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+#set result format/file last
+project -result_file "./MAC_top.vqm"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#par_1 attributes
+set_option -job par_1 -add par
+set_option -job par_1 -option run_backannotation 0
+impl -active "syn"
diff --git a/opencores/ethernet_tri_mode/syn/syn_altrea.prj b/opencores/ethernet_tri_mode/syn/syn_altrea.prj
new file mode 100644
index 000000000..e227ea672
--- /dev/null
+++ b/opencores/ethernet_tri_mode/syn/syn_altrea.prj
@@ -0,0 +1,91 @@
+#-- Synplicity, Inc.
+#-- Version Synplify Pro 8.1
+#-- Project file D:\root\home\ethernet_tri_mode\syn\syn_altrea.prj
+#-- Written on Sun Jun 25 09:40:49 2006
+
+
+#add_file options
+add_file -verilog "../rtl/verilog/header.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"
+add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v"
+add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v"
+add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v"
+add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v"
+add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v"
+add_file -verilog "../rtl/verilog/RMON.v"
+add_file -verilog "../rtl/verilog/MAC_rx.v"
+add_file -verilog "../rtl/verilog/MAC_tx.v"
+add_file -verilog "../rtl/verilog/miim/eth_clockgen.v"
+add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v"
+add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v"
+add_file -verilog "../rtl/verilog/miim/timescale.v"
+add_file -verilog "../rtl/verilog/TECH/altera/duram.v"
+add_file -verilog "../rtl/verilog/TECH/altera/CLK_SWITCH.v"
+add_file -verilog "../rtl/verilog/TECH/altera/CLK_DIV2.v"
+add_file -verilog "../rtl/verilog/eth_miim.v"
+add_file -verilog "../rtl/verilog/Clk_ctrl.v"
+add_file -verilog "../rtl/verilog/Phy_int.v"
+add_file -verilog "../rtl/verilog/Reg_int.v"
+add_file -verilog "../rtl/verilog/MAC_top.v"
+
+
+#implementation: "syn"
+impl -add syn
+
+#device options
+set_option -technology STRATIX
+set_option -part EP1S30
+set_option -package FC780
+set_option -speed_grade -5
+
+#compilation/mapping options
+set_option -default_enum_encoding onehot
+set_option -symbolic_fsm_compiler 0
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+set_option -top_module "MAC_top"
+
+#map options
+set_option -frequency auto
+set_option -run_prop_extract 0
+set_option -fanout_limit 500
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -retiming 0
+set_option -verification_mode 0
+set_option -fixgatedclocks 0
+set_option -no_sequential_opt 0
+
+#simulation options
+set_option -write_verilog 1
+set_option -write_vhdl 0
+
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+#set result format/file last
+project -result_file "./MAC_top.vqm"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -dup 0
+set_option -project_relative_includes 1
+
+#par_1 attributes
+set_option -job par_1 -add par
+set_option -job par_1 -option run_backannotation 0
+impl -active "syn"
diff --git a/opencores/ethernet_tri_mode/syn/syn_xilinx.prj b/opencores/ethernet_tri_mode/syn/syn_xilinx.prj
new file mode 100644
index 000000000..94435b4b1
--- /dev/null
+++ b/opencores/ethernet_tri_mode/syn/syn_xilinx.prj
@@ -0,0 +1,92 @@
+#-- Synplicity, Inc.
+#-- Version Synplify Pro 8.1
+#-- Project file D:\root\home\ethernet_tri_mode\syn\syn_xilinx.prj
+#-- Written on Sun Jun 25 09:43:29 2006
+
+
+#add_file options
+add_file -verilog "../rtl/verilog/header.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_FF.v"
+add_file -verilog "../rtl/verilog/MAC_tx/Ramdon_gen.v"
+add_file -verilog "../rtl/verilog/MAC_tx/CRC_gen.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+add_file -verilog "../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v"
+add_file -verilog "../rtl/verilog/MAC_tx/flow_ctrl.v"
+add_file -verilog "../rtl/verilog/MAC_rx/CRC_chk.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_FF.v"
+add_file -verilog "../rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_addr_gen.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_ctrl.v"
+add_file -verilog "../rtl/verilog/RMON/RMON_dpram.v"
+add_file -verilog "../rtl/verilog/MAC_rx/Broadcast_filter.v"
+add_file -verilog "../rtl/verilog/RMON.v"
+add_file -verilog "../rtl/verilog/MAC_rx.v"
+add_file -verilog "../rtl/verilog/MAC_tx.v"
+add_file -verilog "../rtl/verilog/miim/eth_clockgen.v"
+add_file -verilog "../rtl/verilog/miim/eth_outputcontrol.v"
+add_file -verilog "../rtl/verilog/miim/eth_shiftreg.v"
+add_file -verilog "../rtl/verilog/miim/timescale.v"
+add_file -verilog "../rtl/verilog/TECH/xilinx/duram.v"
+add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_SWITCH.v"
+add_file -verilog "../rtl/verilog/TECH/xilinx/CLK_DIV2.v"
+add_file -verilog "../rtl/verilog/eth_miim.v"
+add_file -verilog "../rtl/verilog/Clk_ctrl.v"
+add_file -verilog "../rtl/verilog/Phy_int.v"
+add_file -verilog "../rtl/verilog/Reg_int.v"
+add_file -verilog "../rtl/verilog/MAC_top.v"
+
+
+#implementation: "syn"
+impl -add syn
+
+#device options
+set_option -technology VIRTEX4
+set_option -part XC4VLX40
+set_option -package FF668
+set_option -speed_grade -10
+
+#compilation/mapping options
+set_option -default_enum_encoding onehot
+set_option -symbolic_fsm_compiler 0
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+set_option -top_module "MAC_top"
+
+#map options
+set_option -frequency auto
+set_option -run_prop_extract 0
+set_option -fanout_limit 10000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -fixgatedclocks 0
+set_option -modular 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+
+#simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+#VIF options
+set_option -write_vif 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+#set result format/file last
+project -result_file "./MAC_top.edf"
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -dup 0
+set_option -project_relative_includes 1
+
+#par_1 attributes
+set_option -job par_1 -add par
+set_option -job par_1 -option run_backannotation 0
+impl -active "syn"