diff options
| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /opencores/ethernet_tri_mode/sim | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'opencores/ethernet_tri_mode/sim')
66 files changed, 1464 insertions, 0 deletions
diff --git a/opencores/ethernet_tri_mode/sim/CVS/Entries b/opencores/ethernet_tri_mode/sim/CVS/Entries new file mode 100644 index 000000000..9487498ad --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/CVS/Entries @@ -0,0 +1 @@ +D/rtl_sim//// diff --git a/opencores/ethernet_tri_mode/sim/CVS/Repository b/opencores/ethernet_tri_mode/sim/CVS/Repository new file mode 100644 index 000000000..cd76b9556 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim diff --git a/opencores/ethernet_tri_mode/sim/CVS/Root b/opencores/ethernet_tri_mode/sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/CVS/Template b/opencores/ethernet_tri_mode/sim/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries b/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries new file mode 100644 index 000000000..110ed0af2 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries @@ -0,0 +1 @@ +D/ncsim_sim//// diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Repository b/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Repository new file mode 100644 index 000000000..930bcb3d9 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Root b/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Template b/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries new file mode 100644 index 000000000..08bef4ec9 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries @@ -0,0 +1,6 @@ +D/bin//// +D/data//// +D/log//// +D/out//// +D/run//// +D/script//// diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Repository b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Repository new file mode 100644 index 000000000..06f0c5682 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Root b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Template b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Entries b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Entries new file mode 100644 index 000000000..75c10e887 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Entries @@ -0,0 +1,12 @@ +/cds.lib/1.2/Thu Jan 19 14:07:56 2006// +/com.nc/1.2/Fri Jan 20 12:18:05 2006// +/config.ini/1.1/Tue Dec 13 12:54:51 2005// +/hdl.var/1.1/Tue Dec 13 12:54:51 2005// +/ip_32W_check.dll/1.1/Thu Jan 19 14:07:56 2006/-kb/ +/ip_32W_check_vpi.dll/1.1/Tue Dec 13 12:54:51 2005/-kb/ +/ip_32W_gen.dll/1.1/Thu Jan 19 14:07:56 2006/-kb/ +/ip_32W_gen_vpi.dll/1.1/Tue Dec 13 12:54:51 2005/-kb/ +/sim.nc/1.3/Fri Jan 20 12:18:05 2006// +/sim_only.nc/1.1/Thu Jan 19 14:07:56 2006// +/vlog.list/1.2/Thu Jan 19 14:07:56 2006// +D diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Repository b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Repository new file mode 100644 index 000000000..f3861d090 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Root b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Template b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/cds.lib b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/cds.lib new file mode 100644 index 000000000..c8b8c7c85 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/cds.lib @@ -0,0 +1,2 @@ +DEFINE work ./worknc + diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/com.nc b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/com.nc new file mode 100644 index 000000000..566452b80 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/com.nc @@ -0,0 +1,36 @@ +if test -d worknc +then +echo worknc is ready +else +mkdir worknc +echo worknc is created +fi + +ncvlog -f vlog.list -logfile ../log/ncvlog.log + +if test $? -ne 0 +then +echo compiling err occured... +exit 1 +fi + +ncelab work.tb_top -NEVERWARN -loadvpi ip_32W_gen:PLI_register -loadvpi ip_32W_check:PLI_register -snapshot work:snap -timescale 1ns/1ps -message -access +rw -logfile ../log/ncelab.log + +if test $? -ne 0 +then +echo ncelab err occured... +exit 1 +fi + +if test -f ../log/.sim_failed +then + echo "../log/.sim_failed log file has been removed!" + rm ../log/.sim_failed +fi + +if test -f ../log/sim_succeed +then + echo "../log/sim_succeed log file has been removed!" + rm ../log/sim_succeed +fi + diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/config.ini b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/config.ini new file mode 100644 index 000000000..cbcc5a0d8 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/config.ini @@ -0,0 +1,3 @@ +46,1500,1,0 + +#Pkt_begin_length,Pkt_end_length,Pkt_number,Random_en diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/hdl.var b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/hdl.var new file mode 100644 index 000000000..1899fceae --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/hdl.var @@ -0,0 +1 @@ +DEFINE WORK work diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll Binary files differnew file mode 100644 index 000000000..675f2fed2 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check.dll diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll Binary files differnew file mode 100644 index 000000000..1b905b7e4 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_check_vpi.dll diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll Binary files differnew file mode 100644 index 000000000..9afbaed18 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen.dll diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll Binary files differnew file mode 100644 index 000000000..04d3b84a8 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/ip_32W_gen_vpi.dll diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim.nc b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim.nc new file mode 100644 index 000000000..6d38346af --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim.nc @@ -0,0 +1,37 @@ +if test -d worknc +then +echo worknc is ready +else +mkdir worknc +echo worknc is created +fi + +ncvlog -f vlog.list -logfile ../log/ncvlog.log + +if test $? -ne 0 +then +echo compiling err occured... +exit 1 +fi + +ncelab work.tb_top -NEVERWARN -loadvpi ip_32W_gen:PLI_register -loadvpi ip_32W_check:PLI_register -snapshot work:snap -timescale 1ns/1ps -message -access +rw -logfile ../log/ncelab.log + +if test $? -ne 0 +then +echo ncelab err occured... +exit 1 +fi + +if test -f ../log/.sim_failed +then + echo "../log/.sim_failed log file has been removed!" + rm ../log/.sim_failed +fi + +if test -f ../log/sim_succeed +then + echo "../log/sim_succeed log file has been removed!" + rm ../log/sim_succeed +fi + +ncsim work:snap $1 -UNBUFFERED -logfile ../log/ncsim.log -NOKEY diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim_only.nc b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim_only.nc new file mode 100644 index 000000000..feae8e7d8 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/sim_only.nc @@ -0,0 +1,13 @@ +if test -f ../log/.sim_failed +then + echo "../log/.sim_failed log file has been removed!" + rm ../log/.sim_failed +fi + +if test -f ../log/sim_succeed +then + echo "../log/sim_succeed log file has been removed!" + rm ../log/sim_succeed +fi + +ncsim work:snap $1 -UNBUFFERED -logfile ../log/ncsim.log -NOKEY diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/vlog.list b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/vlog.list new file mode 100644 index 000000000..a937c8438 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/bin/vlog.list @@ -0,0 +1,41 @@ +../../../../rtl/verilog/header.v + +../../../../rtl/verilog/TECH/CLK_SWITCH.v +../../../../rtl/verilog/TECH/CLK_DIV2.v +../../../../rtl/verilog/TECH/duram.v + +../../../../rtl/verilog/MAC_tx/MAC_tx_FF.v +../../../../rtl/verilog/MAC_tx/Ramdon_gen.v +../../../../rtl/verilog/MAC_tx/CRC_gen.v +../../../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v +../../../../rtl/verilog/MAC_tx/MAC_tx_Ctrl.v +../../../../rtl/verilog/MAC_tx/flow_ctrl.v + +../../../../rtl/verilog/MAC_rx/CRC_chk.v +../../../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v +../../../../rtl/verilog/MAC_rx/MAC_rx_FF.v +../../../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v +../../../../rtl/verilog/MAC_rx/Broadcast_filter.v + +../../../../rtl/verilog/miim/eth_clockgen.v +../../../../rtl/verilog/miim/eth_outputcontrol.v +../../../../rtl/verilog/miim/eth_shiftreg.v + +../../../../rtl/verilog/RMON/RMON_addr_gen.v +../../../../rtl/verilog/RMON/RMON_ctrl.v +../../../../rtl/verilog/RMON/RMON_dpram.v + +../../../../rtl/verilog/RMON.v +../../../../rtl/verilog/MAC_rx.v +../../../../rtl/verilog/MAC_tx.v +../../../../rtl/verilog/eth_miim.v +../../../../rtl/verilog/MAC_top.v +../../../../rtl/verilog/Phy_int.v +../../../../rtl/verilog/Clk_ctrl.v +../../../../rtl/verilog/Reg_int.v + +../../../../bench/verilog/altera_mf.v +../../../../bench/verilog/Phy_sim.v +../../../../bench/verilog/User_int_sim.v +../../../../bench/verilog/host_sim.v +../../../../bench/verilog/tb_top.v diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec new file mode 100644 index 000000000..364183597 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/1000Mbps_duplex.vec @@ -0,0 +1 @@ +01200004 diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec new file mode 100644 index 000000000..b4f602f88 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/100Mbps_duplex.vec @@ -0,0 +1 @@ +01200002 diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec new file mode 100644 index 000000000..a3b941871 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/10Mbps_duplex.vec @@ -0,0 +1 @@ +01200001 diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/46-50.ini b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/46-50.ini new file mode 100644 index 000000000..313b49c77 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/46-50.ini @@ -0,0 +1 @@ +46,50,1,0 diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CPU.vec b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CPU.vec new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CPU.vec diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Entries b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Entries new file mode 100644 index 000000000..0df4c0792 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Entries @@ -0,0 +1,11 @@ +/1000Mbps_duplex.vec/1.1/Thu Jan 19 14:07:57 2006// +/100Mbps_duplex.vec/1.1/Thu Jan 19 14:07:57 2006// +/10Mbps_duplex.vec/1.1/Thu Jan 19 14:07:57 2006// +/46-50.ini/1.1/Thu Jan 19 14:07:57 2006// +/CPU.vec/1.1/Thu Jan 19 14:07:57 2006// +/batch.dat/1.1/Thu Jan 19 14:07:57 2006// +/config.ini/1.2/Sun Jun 25 04:58:57 2006// +/flow_ctrl.vec/1.1/Thu Jan 19 14:07:57 2006// +/source_mac_replace.vec/1.1/Thu Jan 19 14:07:57 2006// +/target_mac_check.vec/1.1/Thu Jan 19 14:07:57 2006// +D diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Repository b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Repository new file mode 100644 index 000000000..cc9effe3f --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Root b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Template b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/batch.dat b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/batch.dat new file mode 100644 index 000000000..a37f5040a --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/batch.dat @@ -0,0 +1,3 @@ +{1000Mbps mode 46-80 length packet testcase} 46-50.ini 1000Mbps_duplex.vec +{100 Mbps mode 46-50 length packet testcase} 46-50.ini 100Mbps_duplex.vec +{10 Mbps mode 46-50 length packet testcase} 46-50.ini 10Mbps_duplex.vec diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/config.ini b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/config.ini new file mode 100644 index 000000000..cd64f1692 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/config.ini @@ -0,0 +1 @@ +46,1500,1,0,0 diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec new file mode 100644 index 000000000..978689ab0 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/flow_ctrl.vec @@ -0,0 +1,4 @@ +04020001 +0403000a +040b000a +040c0001 diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec new file mode 100644 index 000000000..f1f498941 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/source_mac_replace.vec @@ -0,0 +1,24 @@ +12070001 +12080030 +120a0001 +180a0000 +18080031 +18090001 +180a0001 +180a0000 +18080032 +18090002 +180a0001 +180a0000 +18080033 +18090003 +180a0001 +180a0000 +18080034 +18090004 +180a0001 +180a0000 +18080035 +18090005 +180a0001 +180a0000 diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec new file mode 100644 index 000000000..71401b15c --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/data/target_mac_check.vec @@ -0,0 +1,25 @@ +190e0001 +190f0010 +19100000 +19110001 +19110000 +190f0011 +19100001 +19110001 +19110000 +190f0012 +19100002 +19110001 +19110000 +190f0013 +19100003 +19110001 +19110000 +190f0014 +19100004 +19110001 +19110000 +190f0016 +19100005 +19110001 +19110000
\ No newline at end of file diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Entries b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Entries new file mode 100644 index 000000000..85b414b74 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Entries @@ -0,0 +1,2 @@ +/ncsim.log/1.3/Fri Nov 17 17:53:07 2006// +D diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Repository b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Repository new file mode 100644 index 000000000..060990863 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Root b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Template b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/ncsim.log b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/ncsim.log new file mode 100644 index 000000000..c2ede5380 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/log/ncsim.log @@ -0,0 +1,245 @@ +ncsim: 05.00-p001: (c) Copyright 1995-2003 Cadence Design Systems, Inc. +////////////////////////////////////////////////////////////////////// +//// +//// $ip_32W_gen is used to generate stimulus with 32bit +//// width ip packet data flow. +//// The only parameter is config.ini file that is used to +//// control the generated packet data flow. +//// +////////////////////////////////////////////////////////////////////// +////////////////////////////////////////////////////////////////////// +//// StartOfSim callback printing info +////////////////////////////////////////////////////////////////////// +ncsim> run + +the NO. 0001 IP Length is:0046 CRC-32check OK! +the NO. 0002 IP Length is:0047 CRC-32check OK! +the NO. 0003 IP Length is:0048 CRC-32check OK! +the NO. 0004 IP Length is:0049 CRC-32check OK! +the NO. 0005 IP Length is:0050 CRC-32check OK! +the NO. 0006 IP Length is:0051 CRC-32check OK! +the NO. 0007 IP Length is:0052 CRC-32check OK! +the NO. 0008 IP Length is:0053 CRC-32check OK! +the NO. 0009 IP Length is:0054 CRC-32check OK! +the NO. 000a IP Length is:0055 CRC-32check OK! +the NO. 000b IP Length is:0056 CRC-32check OK! +the NO. 000c IP Length is:0057 CRC-32check OK! +the NO. 000d IP Length is:0058 CRC-32check OK! +the NO. 000e IP Length is:0059 CRC-32check OK! +the NO. 000f IP Length is:0060 CRC-32check OK! +the NO. 0010 IP Length is:0061 CRC-32check OK! +the NO. 0011 IP Length is:0062 CRC-32check OK! +the NO. 0012 IP Length is:0063 CRC-32check OK! +the NO. 0013 IP Length is:0064 CRC-32check OK! +the NO. 0014 IP Length is:0065 CRC-32check OK! +the NO. 0015 IP Length is:0066 CRC-32check OK! +the NO. 0016 IP Length is:0067 CRC-32check OK! +the NO. 0017 IP Length is:0068 CRC-32check OK! +the NO. 0018 IP Length is:0069 CRC-32check OK! +the NO. 0019 IP Length is:0070 CRC-32check OK! +the NO. 001a IP Length is:0071 CRC-32check OK! +the NO. 001b IP Length is:0072 CRC-32check OK! +the NO. 001c IP Length is:0073 CRC-32check OK! +the NO. 001d IP Length is:0074 CRC-32check OK! +the NO. 001e IP Length is:0075 CRC-32check OK! +the NO. 001f IP Length is:0076 CRC-32check OK! +the NO. 0020 IP Length is:0077 CRC-32check OK! +the NO. 0021 IP Length is:0078 CRC-32check OK! +the NO. 0022 IP Length is:0079 CRC-32check OK! +the NO. 0023 IP Length is:0080 CRC-32check OK! +the NO. 0024 IP Length is:0081 CRC-32check OK! +the NO. 0025 IP Length is:0082 CRC-32check OK! +the NO. 0026 IP Length is:0083 CRC-32check OK! +the NO. 0027 IP Length is:0084 CRC-32check OK! +the NO. 0028 IP Length is:0085 CRC-32check OK! +the NO. 0029 IP Length is:0086 CRC-32check OK! +the NO. 002a IP Length is:0087 CRC-32check OK! +the NO. 002b IP Length is:0088 CRC-32check OK! +the NO. 002c IP Length is:0089 CRC-32check OK! +the NO. 002d IP Length is:0090 CRC-32check OK! +the NO. 002e IP Length is:0091 CRC-32check OK! +the NO. 002f IP Length is:0092 CRC-32check OK! +the NO. 0030 IP Length is:0093 CRC-32check OK! +the NO. 0031 IP Length is:0094 CRC-32check OK! +the NO. 0032 IP Length is:0095 CRC-32check OK! +the NO. 0033 IP Length is:0096 CRC-32check OK! +the NO. 0034 IP Length is:0097 CRC-32check OK! +the NO. 0035 IP Length is:0098 CRC-32check OK! +the NO. 0036 IP Length is:0099 CRC-32check OK! +the NO. 0037 IP Length is:0100 CRC-32check OK! +the NO. 0038 IP Length is:0101 CRC-32check OK! +the NO. 0039 IP Length is:0102 CRC-32check OK! +the NO. 003a IP Length is:0103 CRC-32check OK! +the NO. 003b IP Length is:0104 CRC-32check OK! +the NO. 003c IP Length is:0105 CRC-32check OK! +the NO. 003d IP Length is:0106 CRC-32check OK! +the NO. 003e IP Length is:0107 CRC-32check OK! +the NO. 003f IP Length is:0108 CRC-32check OK! +the NO. 0040 IP Length is:0109 CRC-32check OK! +the NO. 0041 IP Length is:0110 CRC-32check OK! +the NO. 0042 IP Length is:0111 CRC-32check OK! +the NO. 0043 IP Length is:0112 CRC-32check OK! +the NO. 0044 IP Length is:0113 CRC-32check OK! +the NO. 0045 IP Length is:0114 CRC-32check OK! +the NO. 0046 IP Length is:0115 CRC-32check OK! +the NO. 0047 IP Length is:0116 CRC-32check OK! +the NO. 0048 IP Length is:0117 CRC-32check OK! +the NO. 0049 IP Length is:0118 CRC-32check OK! +the NO. 004a IP Length is:0119 CRC-32check OK! +the NO. 004b IP Length is:0120 CRC-32check OK! +the NO. 004c IP Length is:0121 CRC-32check OK! +the NO. 004d IP Length is:0122 CRC-32check OK! +the NO. 004e IP Length is:0123 CRC-32check OK! +the NO. 004f IP Length is:0124 CRC-32check OK! +the NO. 0050 IP Length is:0125 CRC-32check OK! +the NO. 0051 IP Length is:0126 CRC-32check OK! +the NO. 0052 IP Length is:0127 CRC-32check OK! +the NO. 0053 IP Length is:0128 CRC-32check OK! +the NO. 0054 IP Length is:0129 CRC-32check OK! +the NO. 0055 IP Length is:0130 CRC-32check OK! +the NO. 0056 IP Length is:0131 CRC-32check OK! +the NO. 0057 IP Length is:0132 CRC-32check OK! +the NO. 0058 IP Length is:0133 CRC-32check OK! +the NO. 0059 IP Length is:0134 CRC-32check OK! +the NO. 005a IP Length is:0135 CRC-32check OK! +the NO. 005b IP Length is:0136 CRC-32check OK! +the NO. 005c IP Length is:0137 CRC-32check OK! +the NO. 005d IP Length is:0138 CRC-32check OK! +the NO. 005e IP Length is:0139 CRC-32check OK! +the NO. 005f IP Length is:0140 CRC-32check OK! +the NO. 0060 IP Length is:0141 CRC-32check OK! +the NO. 0061 IP Length is:0142 CRC-32check OK! +the NO. 0062 IP Length is:0143 CRC-32check OK! +the NO. 0063 IP Length is:0144 CRC-32check OK! +the NO. 0064 IP Length is:0145 CRC-32check OK! +the NO. 0065 IP Length is:0146 CRC-32check OK! +the NO. 0066 IP Length is:0147 CRC-32check OK! +the NO. 0067 IP Length is:0148 CRC-32check OK! +the NO. 0068 IP Length is:0149 CRC-32check OK! +the NO. 0069 IP Length is:0150 CRC-32check OK! +the NO. 006a IP Length is:0151 CRC-32check OK! +the NO. 006b IP Length is:0152 CRC-32check OK! +the NO. 006c IP Length is:0153 CRC-32check OK! +the NO. 006d IP Length is:0154 CRC-32check OK! +the NO. 006e IP Length is:0155 CRC-32check OK! +the NO. 006f IP Length is:0156 CRC-32check OK! +the NO. 0070 IP Length is:0157 CRC-32check OK! +the NO. 0071 IP Length is:0158 CRC-32check OK! +the NO. 0072 IP Length is:0159 CRC-32check OK! +the NO. 0073 IP Length is:0160 CRC-32check OK! +the NO. 0074 IP Length is:0161 CRC-32check OK! +the NO. 0075 IP Length is:0162 CRC-32check OK! +the NO. 0076 IP Length is:0163 CRC-32check OK! +the NO. 0077 IP Length is:0164 CRC-32check OK! +the NO. 0078 IP Length is:0165 CRC-32check OK! +the NO. 0079 IP Length is:0166 CRC-32check OK! +the NO. 007a IP Length is:0167 CRC-32check OK! +the NO. 007b IP Length is:0168 CRC-32check OK! +the NO. 007c IP Length is:0169 CRC-32check OK! +the NO. 007d IP Length is:0170 CRC-32check OK! +the NO. 007e IP Length is:0171 CRC-32check OK! +the NO. 007f IP Length is:0172 CRC-32check OK! +the NO. 0080 IP Length is:0173 CRC-32check OK! +the NO. 0081 IP Length is:0174 CRC-32check OK! +the NO. 0082 IP Length is:0175 CRC-32check OK! +the NO. 0083 IP Length is:0176 CRC-32check OK! +the NO. 0084 IP Length is:0177 CRC-32check OK! +the NO. 0085 IP Length is:0178 CRC-32check OK! +the NO. 0086 IP Length is:0179 CRC-32check OK! +the NO. 0087 IP Length is:0180 CRC-32check OK! +the NO. 0088 IP Length is:0181 CRC-32check OK! +the NO. 0089 IP Length is:0182 CRC-32check OK! +the NO. 008a IP Length is:0183 CRC-32check OK! +the NO. 008b IP Length is:0184 CRC-32check OK! +the NO. 008c IP Length is:0185 CRC-32check OK! +the NO. 008d IP Length is:0186 CRC-32check OK! +the NO. 008e IP Length is:0187 CRC-32check OK! +the NO. 008f IP Length is:0188 CRC-32check OK! +the NO. 0090 IP Length is:0189 CRC-32check OK! +the NO. 0091 IP Length is:0190 CRC-32check OK! +the NO. 0092 IP Length is:0191 CRC-32check OK! +the NO. 0093 IP Length is:0192 CRC-32check OK! +the NO. 0094 IP Length is:0193 CRC-32check OK! +the NO. 0095 IP Length is:0194 CRC-32check OK! +the NO. 0096 IP Length is:0195 CRC-32check OK! +the NO. 0097 IP Length is:0196 CRC-32check OK! +the NO. 0098 IP Length is:0197 CRC-32check OK! +the NO. 0099 IP Length is:0198 CRC-32check OK! +the NO. 009a IP Length is:0199 CRC-32check OK! +the NO. 009b IP Length is:0200 CRC-32check OK! +the NO. 009c IP Length is:0201 CRC-32check OK! +the NO. 009d IP Length is:0202 CRC-32check OK! +the NO. 009e IP Length is:0203 CRC-32check OK! +the NO. 009f IP Length is:0204 CRC-32check OK! +the NO. 00a0 IP Length is:0205 CRC-32check OK! +the NO. 00a1 IP Length is:0206 CRC-32check OK! +the NO. 00a2 IP Length is:0207 CRC-32check OK! +the NO. 00a3 IP Length is:0208 CRC-32check OK! +the NO. 00a4 IP Length is:0209 CRC-32check OK! +the NO. 00a5 IP Length is:0210 CRC-32check OK! +the NO. 00a6 IP Length is:0211 CRC-32check OK! +the NO. 00a7 IP Length is:0212 CRC-32check OK! +the NO. 00a8 IP Length is:0213 CRC-32check OK! +the NO. 00a9 IP Length is:0214 CRC-32check OK! +the NO. 00aa IP Length is:0215 CRC-32check OK! +the NO. 00ab IP Length is:0216 CRC-32check OK! +the NO. 00ac IP Length is:0217 CRC-32check OK! +the NO. 00ad IP Length is:0218 CRC-32check OK! +the NO. 00ae IP Length is:0219 CRC-32check OK! +the NO. 00af IP Length is:0220 CRC-32check OK! +the NO. 00b0 IP Length is:0221 CRC-32check OK! +the NO. 00b1 IP Length is:0222 CRC-32check OK! +the NO. 00b2 IP Length is:0223 CRC-32check OK! +the NO. 00b3 IP Length is:0224 CRC-32check OK! +the NO. 00b4 IP Length is:0225 CRC-32check OK! +the NO. 00b5 IP Length is:0226 CRC-32check OK! +the NO. 00b6 IP Length is:0227 CRC-32check OK! +the NO. 00b7 IP Length is:0228 CRC-32check OK! +the NO. 00b8 IP Length is:0229 CRC-32check OK! +the NO. 00b9 IP Length is:0230 CRC-32check OK! +the NO. 00ba IP Length is:0231 CRC-32check OK! +the NO. 00bb IP Length is:0232 CRC-32check OK! +the NO. 00bc IP Length is:0233 CRC-32check OK! +the NO. 00bd IP Length is:0234 CRC-32check OK! +the NO. 00be IP Length is:0235 CRC-32check OK! +the NO. 00bf IP Length is:0236 CRC-32check OK! +the NO. 00c0 IP Length is:0237 CRC-32check OK! +the NO. 00c1 IP Length is:0238 CRC-32check OK! +the NO. 00c2 IP Length is:0239 CRC-32check OK! +the NO. 00c3 IP Length is:0240 CRC-32check OK! +the NO. 00c4 IP Length is:0241 CRC-32check OK! +the NO. 00c5 IP Length is:0242 CRC-32check OK! +the NO. 00c6 IP Length is:0243 CRC-32check OK! +the NO. 00c7 IP Length is:0244 CRC-32check OK! +the NO. 00c8 IP Length is:0245 CRC-32check OK! +the NO. 00c9 IP Length is:0246 CRC-32check OK! +the NO. 00ca IP Length is:0247 CRC-32check OK! +the NO. 00cb IP Length is:0248 CRC-32check OK! +the NO. 00cc IP Length is:0249 CRC-32check OK! +the NO. 00cd IP Length is:0250 CRC-32check OK! +the NO. 00ce IP Length is:0251 CRC-32check OK! +the NO. 00cf IP Length is:0252 CRC-32check OK! +the NO. 00d0 IP Length is:0253 CRC-32check OK! +the NO. 00d1 IP Length is:0254 CRC-32check OK! +the NO. 00d2 IP Length is:0255 CRC-32check OK! +the NO. 00d3 IP Length is:0256 CRC-32check OK! +the NO. 00d4 IP Length is:0257 CRC-32check OK! +the NO. 00d5 IP Length is:0258 CRC-32check OK! +the NO. 00d6 IP Length is:0259 CRC-32check OK! +the NO. 00d7 IP Length is:0260 CRC-32check OK! +the NO. 00d8 IP Length is:0261 CRC-32check OK! +the NO. 00d9 IP Length is:0262 CRC-32check OK! +the NO. 00da IP Length is:0263 CRC-32check OK! +the NO. 00db IP Length is:0264 CRC-32check OK! +the NO. 00dc IP Length is:0265 CRC-32check OK! +the NO. 00dd IP Length is:0266 CRC-32check OK! +the NO. 00de IP Length is:0267 CRC-32check OK! +the NO. 00df IP Length is:0268 CRC-32check OK! +the NO. 00e0 IP Length is:0269 CRC-32check OK! +the NO. 00e1 IP Length is:0270 CRC-32check OK! +the NO. 00e2 IP Length is:0271 CRC-32check OK! +the NO. 00e3 IP Length is:0272 CRC-32check OK! +the NO. 00e4 IP Length is:0273 CRC-32check OK! +the NO. 00e5 IP Length is:0274 CRC-32check OK! +the NO. 00e6 IP Length is:0275 CRC-32check OK!Simulation interrupted at 367372 NS + 0 +ncsim> exit diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Entries b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Repository b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Repository new file mode 100644 index 000000000..46dd9edc2 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Root b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Template b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/out/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Entries b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Entries new file mode 100644 index 000000000..178481050 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Entries @@ -0,0 +1 @@ +D diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Repository b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Repository new file mode 100644 index 000000000..90f699204 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Root b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Template b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/run/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Entries b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Entries new file mode 100644 index 000000000..4ca22003b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Entries @@ -0,0 +1,9 @@ +/batch_mode.tcl/1.2/Thu Apr 6 13:12:05 2006// +/filesel.tcl/1.1/Thu Jan 19 16:18:28 2006// +/run.tcl/1.1/Thu Jan 19 16:18:28 2006// +/run_proc.tcl/1.2/Thu Apr 6 13:12:05 2006// +/set_reg_data.tcl/1.3/Thu Apr 6 13:12:05 2006// +/set_stimulus.tcl/1.2/Thu Apr 6 13:12:05 2006// +/start_verify.tcl/1.2/Thu Apr 6 13:12:05 2006// +/user_lib.tcl/1.2/Thu Apr 6 13:12:05 2006// +D diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Repository b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Repository new file mode 100644 index 000000000..7e86a1503 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Repository @@ -0,0 +1 @@ +ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Root b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Root new file mode 100644 index 000000000..44b2aa23b --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Root @@ -0,0 +1 @@ +:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Template b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Template new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/CVS/Template diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl new file mode 100644 index 000000000..9185aded4 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/batch_mode.tcl @@ -0,0 +1,148 @@ +proc batch_mode {} { +variable i +variable index empty +variable batch_data +set namelist \ +{- Description Stimulus RegVector} +############################################################################### + toplevel .b + wm title .b "Setting Reg Data" + focus .b + frame .b.f100 + + set lth1 20 + set lth2 15 + set lth3 15 + cd ../data + if {[catch {open batch.dat r} fileid]} { + break + } else { + set batch_data {} + gets $fileid line + while {[eof $fileid]==0} { + lappend batch_data $line + if {[string length [lindex $line 0]] > $lth1 } { + set lth1 [string length [lindex $line 0]] + } + if {[string length [lindex $line 1]] > $lth2 } { + set lth2 [string length [lindex $line 1]] + } + if {[string length [lindex $line 2]] > $lth3 } { + set lth3 [string length [lindex $line 2]] + } + gets $fileid line + } + close $fileid + } + + label .b.f100.l1 -text [lindex $namelist 0] -fg blue -width 5 + label .b.f100.l2 -text [lindex $namelist 1] -fg blue -width [expr $lth1 +5] + label .b.f100.l3 -text [lindex $namelist 2] -fg blue -width [expr $lth2 +5] + label .b.f100.l4 -text [lindex $namelist 3] -fg blue -width [expr $lth3 +5] + pack .b.f100 + pack .b.f100.l1 .b.f100.l2 .b.f100.l3 .b.f100.l4 -side left + + set i 0 + foreach line $batch_data { + frame .b.f$i + set tmp [expr $i+1] + checkbutton .b.f$i.c -variable check$i -text $tmp -width 5 + label .b.f$i.l1 -text [lindex $line 0] -width $lth1 + button .b.f$i.b1 -text "Change" -width 5 -command [list ChangeDescript .b.f$i.l1 $i 0] + label .b.f$i.l2 -text [lindex $line 1] -width $lth2 + button .b.f$i.b2 -text "Change" -width 5 -command [list ChangeLabel .b.f$i.l2 $i 1] + label .b.f$i.l3 -text [lindex $line 2] -width $lth3 + button .b.f$i.b3 -text "Change" -width 5 -command [list ChangeLabel .b.f$i.l3 $i 2] + pack .b.f$i + pack .b.f$i.c .b.f$i.l1 .b.f$i.b1 .b.f$i.l2 .b.f$i.b2 .b.f$i.l3 .b.f$i.b3 -side left + incr i + } + + + frame .b.f102 + button .b.f102.b1 -text "Start Verify" -width 10 + button .b.f102.b2 -text "Save" -width 10 -command {save_batch_data} + button .b.f102.b3 -text "Exit" -width 10 -command {destroy .b} + pack .b.f102 + pack .b.f102.b1 .b.f102.b2 .b.f102.b3 -side left + bind .b.f102.b1 <ButtonPress> {create_index $i} + bind .b.f102.b1 <ButtonRelease> {start_verify 1 $index} +} + +proc create_index {i} { + global index + set index empty + set sim_times 0 + save_batch_data + for {set c 0} {$c < $i} {incr c} { + upvar 1 check$c tmp + if {$tmp==1 && $sim_times==0} { + set index $c + incr sim_times + } elseif {$tmp==1} { + lappend index $c + incr sim_times + } + } +} + +proc ChangeLabel {target_label y x} { + global batch_data + global fileselect + fileselect + tkwait window .fileSelectWindow + if {$fileselect(canceled)==1} { + return + } elseif {$fileselect(selectedfile)==""} { + warning_message "file have not been selected!" + } else { + $target_label config -text $fileselect(selectedfile) + set line [lindex $batch_data $y] + set line [lreplace $line $x $x $fileselect(selectedfile)] + set batch_data [lreplace $batch_data $y $y $line] + } +} + +proc save_batch_data {} { + global batch_data + if {[catch {open batch.dat w} fileid]} { + break + } else { + foreach line $batch_data { + puts $fileid $line + } + close $fileid + } +} + +proc ChangeDescript {target_label y x} { + global batch_data + variable value + variable target + variable newy + variable newx + toplevel .tmp + focus .tmp + set target $target_label + set newy $y + set newx $x + entry .tmp.en -width 20 -textvariable value + button .tmp.b -width 5 -text "Apply" -command {destroy .tmp} + button .tmp.b1 -width 5 -text "quit" + bind .tmp.b <ButtonPress> {ChangeDescriptApply $target $newy $newx $value} + + + pack .tmp.en .tmp.b +} + +proc ChangeDescriptApply {target_label y x value} { + global batch_data + if {$value==""} { + warning_message "Description can not be empty" + } else { + $target_label config -text $value + set line [lindex $batch_data $y] + set line [lreplace $line 0 0 $value] + set batch_data [lreplace $batch_data $y $y $line] + } +}
\ No newline at end of file diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/filesel.tcl b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/filesel.tcl new file mode 100644 index 000000000..c300a4403 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/filesel.tcl @@ -0,0 +1,325 @@ +# +# fileselect.tcl -- +# simple file selector. +# +# Mario Jorge Silva msilva@cs.Berkeley.EDU +# University of California Berkeley Ph: +1(510)642-8248 +# Computer Science Division, 571 Evans Hall Fax: +1(510)642-5775 +# Berkeley CA 94720 +# + +# Layout: +# +# file: +----+ +# ____________________ | OK | +# +----+ +# +# +------------------+ Cancel +# | .. |S +# | file1 |c +# | file2 |r +# | |b +# | filen |a +# | |r +# +------------------+ +# currrent-directory +# +# Copyright 1993 Regents of the University of California +# Permission to use, copy, modify, and distribute this +# software and its documentation for any purpose and without +# fee is hereby granted, provided that this copyright +# notice appears in all copies. The University of California +# makes no representations about the suitability of this +# software for any purpose. It is provided "as is" without +# express or implied warranty. +# + +# Copyright 1996 + +# Slight modifications to and adoption to Tk4.0 were made to this +# fileselectionbox code by Lakshmi Sastry, Rutherford Appleton Laboratory, +# chilton, Didcot, OXON, OX11 0QX, UK. + +# You can now type in a non-existing file name as well. This file name is +# returned for the application to open a new file to write to + +# AGOCG Tcl/Tk Cookbook +# Authors + +# Lakshmi Sastry +# Computing and Information Systems Department +# Rutherford Appleton Laboratory, Chilton, Didcot. OX11 0QX +# lakshmi.sastry@rl.ac.uk + +# and + +# Venkat VSS Sastry +# Department of Applied Mathematics and Operational Research +# Cranfield University, RMCS Shrivenham, Swindon, SN6 8LA +# sastry@rmcs.cran.ac.uk + +# Permission to use, copy, modify, and distribute this +# software and its documentation for any purpose and without +# fee is hereby granted, provided that this copyright +# notice appears in all copies. + +# The authors, RAL, RMCS Shrivenham, Cranfield University and AGOCG +# make no representations about the suitability of this +# software for any purpose. It is provided "as is" without +# express or implied warranty. Likewise they accept no responsibility +# whatsoever for any public domain software modules used (which are +# hereby acknowledged) in this software + + +# names starting with "fileselect" are reserved by this module +# no other names used. + +# use the "option" command for further configuration + +option add *Listbox*font \ + "-*-helvetica-medium-r-normal-*-12-*-*-*-p-*-iso8859-1" startupFile +option add *Entry*font \ + "-*-helvetica-medium-r-normal-*-12-*-*-*-p-*-iso8859-1" startupFile +option add *Label*font \ + "-*-helvetica-medium-r-normal-*-12-*-*-*-p-*-iso8859-1" startupFile + + +# this is the default proc called when "OK" is pressed +# to indicate yours, give it as the first arg to "fileselect" + +proc fileselect.default.cmd {f} { +global fileselect +set fileselect(selectedfile) $f +set fileselect(canceled) 0 +#puts stderr "selected file $f" + +} + + +# this is the default proc called when error is detected +# indicate your own pro as an argument to fileselect + +proc fileselect.default.errorHandler {errorMessage} { + puts stdout "error: $errorMessage" + catch { cd ~ } +} + +# this is the proc that creates the file selector box + +proc fileselect { + {cmd fileselect.default.cmd} + {purpose "Open file:"} + {w .fileSelectWindow} + {errorHandler fileselect.default.errorHandler}} { + + catch {destroy $w} + + toplevel $w + grab $w + wm title $w "Select File" + + + # path independent names for the widgets + global fileselect + global selected + set fileselect(entry) $w.file.eframe.entry + set fileselect(list) $w.file.sframe.list + set fileselect(scroll) $w.file.sframe.scroll + set fileselect(ok) $w.bframe.okframe.ok + set fileselect(cancel) $w.bframe.cancel + set fileselect(dirlabel) $w.file.dirlabel + + # widgets + frame $w.file -bd 10 + frame $w.bframe -bd 10 + pack append $w \ + $w.file {left filly} \ + $w.bframe {left expand frame n} + + frame $w.file.eframe + frame $w.file.sframe + label $w.file.dirlabel -anchor e -width 24 -text [pwd] + + pack append $w.file \ + $w.file.eframe {top frame w} \ + $w.file.sframe {top fillx} \ + $w.file.dirlabel {top frame w} + + + label $w.file.eframe.label -anchor w -width 24 -text $purpose + entry $w.file.eframe.entry -relief sunken + + pack append $w.file.eframe \ + $w.file.eframe.label {top expand frame w} \ + $w.file.eframe.entry {top fillx frame w} + + + scrollbar $w.file.sframe.yscroll -relief sunken \ + -command "$w.file.sframe.list yview" + listbox $w.file.sframe.list -relief sunken -selectmode single \ + -yscroll "$w.file.sframe.yscroll set" + #$fileselect(list) configure -selectmode single + pack append $w.file.sframe \ + $w.file.sframe.yscroll {right filly} \ + $w.file.sframe.list {left expand fill} + + # buttons + frame $w.bframe.okframe -borderwidth 2 -relief sunken + + button $w.bframe.okframe.ok -text OK -relief raised -padx 10 \ + -command "fileselect.ok.cmd $w $cmd $errorHandler" + + button $w.bframe.cancel -text cancel -relief raised -padx 10 \ + -command "fileselect.cancel.cmd $w" + pack append $w.bframe.okframe $w.bframe.okframe.ok {padx 10 pady 10} + + pack append $w.bframe $w.bframe.okframe {expand padx 20 pady 20}\ + $w.bframe.cancel {top} + + # Fill the listbox with a list of the files in the directory (run + # the "/bin/ls" command to get that information). + # to not display the "." files, remove the -a option and fileselect + # will still work + + $fileselect(list) insert end ".." + foreach i [exec ls -a [pwd]] { + if {[string compare $i "."] != 0 && \ + [string compare $i ".."] != 0 } { + $fileselect(list) insert end $i + } + } + + # Set up bindings for the browser. + bind $fileselect(entry) <Return> {eval $fileselect(ok) invoke} + bind $fileselect(entry) <Control-c> {eval $fileselect(cancel) invoke} + + bind $fileselect(list) <Button-1> { + # puts stderr "button 1 release" + set x [$fileselect(list) curselection] + $fileselect(entry) delete 0 end + $fileselect(entry) insert 0 [%W get [%W nearest %y]] + } + + bind $fileselect(list) <Key> { + set x [$fileselect(list) curselection] + $fileselect(entry) delete 0 end + $fileselect(entry) insert 0 [%W get [%W nearest %y]] + } + + bind $fileselect(list) <Double-ButtonPress-1> { + # puts stderr "double button 1" + set x [$fileselect(list) curselection] + $fileselect(entry) delete 0 end + $fileselect(entry) insert 0 [%W get [%W nearest %y]] + $fileselect(ok) invoke + } + + bind $fileselect(list) <Return> { + set x [$fileselect(list) curselection] + $fileselect(entry) delete 0 end + $fileselect(entry) insert 0 [%W get [%W nearest %y]] + $fileselect(ok) invoke + } + + # set kbd focus to entry widget + + focus $fileselect(entry) + +} + + +# auxiliary button procedures + +proc fileselect.cancel.cmd {w} { + # puts stderr "Cancel" + global fileselect + set fileselect(canceled) 1 + destroy $w +} + +proc fileselect.ok.cmd {w cmd errorHandler} { + global fileselect + global selected + set selected [$fileselect(entry) get] + # some nasty file names may cause "file isdirectory" to return an error + set sts [catch { + file isdirectory $selected + } errorMessage ] + + if { $sts != 0 } then { + $errorHandler $errorMessage + destroy $w + return + + } + + # clean the text entry and prepare the list + $fileselect(entry) delete 0 end + $fileselect(list) delete 0 end + $fileselect(list) insert end ".." + + # perform globbing on the selection. + # If globing returns an error (no match) check if a non-null name is + # entered. If name string is non-empty return it as a new file name + # else give an error message. + # If resulting list length > 1, put the list on the file listbox and return + # If globing expands to a list of filenames in multiple directories, + # the indicated regexp is invalid and the error handler is called instead. +set globlist 0 + + set sts [catch { + set globlist [glob [list $selected]] + } errorMessage ] + + if { $sts != 0 } then { + if { [llength $globlist] == 1 } { + destroy $w + $cmd $selected + return + } else { + + $errorHandler $errorMessage + destroy $w + return + + } + + + } + + if {[llength $globlist] > 1} { + if {[regexp "/" $globlist] != 0} { + $errorHandler [list "Invalid regular expression, " $selected, "."] + destroy $w + return + } + foreach i $globlist { + if {[string compare $i "."] != 0 && \ + [string compare $i ".."] != 0} { + $fileselect(list) insert end $i + } + } + return + } + + # selection may be a directory. Expand it. + + if {[file isdirectory $selected] != 0} { + cd $selected + set dir [pwd] + $fileselect(dirlabel) configure -text $dir + + foreach i [exec ls -a $dir] { + if {[string compare $i "."] != 0 && \ + [string compare $i ".."] != 0} { + $fileselect(list) insert end $i + } + } + return + } + + destroy $w + $cmd $selected + +} + diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run.tcl b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run.tcl new file mode 100644 index 000000000..ac8a307db --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run.tcl @@ -0,0 +1,26 @@ +source user_lib.tcl +source set_stimulus.tcl +source set_reg_data.tcl +source start_verify.tcl +source batch_mode.tcl +source filesel.tcl + + +wm title . "main" +frame .frame +button .frame.b1 -width 20 -text "set_stimulus" +button .frame.b2 -width 20 -text "set_cpu_data" +button .frame.b3 -width 20 -text "start_verify" +button .frame.b4 -width 20 -text "batch_mode" +button .frame.b40 -width 20 -text "exit" + +bind .frame.b1 <Button-1> {set_stimulus} +bind .frame.b2 <Button-1> {set_reg_data} +bind .frame.b3 <Button-1> {start_verify 0 empty} +bind .frame.b4 <Button-1> {batch_mode} +bind .frame.b40 <Button-1> {exit} + + +pack .frame .frame.b1 .frame.b2 .frame.b3 .frame.b4 .frame.b40 + +
\ No newline at end of file diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run_proc.tcl b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run_proc.tcl new file mode 100644 index 000000000..294cb2c72 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/run_proc.tcl @@ -0,0 +1,27 @@ +proc run_proc {} { +source user_lib.tcl +source set_stimulus.tcl +source set_reg_data.tcl +source start_verify.tcl +source batch_mode.tcl +source filesel.tcl + +toplevel .frame +focus .frame +wm title .frame "main" +button .frame.b1 -width 20 -text "set_stimulus" +button .frame.b2 -width 20 -text "set_cpu_data" +button .frame.b3 -width 20 -text "start_verify" +button .frame.b4 -width 20 -text "batch_mode" +button .frame.b40 -width 20 -text "exit" -command {cd ../../../../ ;destroy .frame} + +bind .frame.b1 <Button-1> {set_stimulus} +bind .frame.b2 <Button-1> {set_reg_data} +bind .frame.b3 <Button-1> {start_verify 0 empty} +bind .frame.b4 <Button-1> {batch_mode} + + + +pack .frame.b1 .frame.b2 .frame.b3 .frame.b4 .frame.b40 + +}
\ No newline at end of file diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl new file mode 100644 index 000000000..b4bfae35d --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_reg_data.tcl @@ -0,0 +1,192 @@ +proc set_reg_data {} { +variable help_strings +variable RegVector +variable datalist +set help_strings { +Set Reg Data: + The verifcation system will config DUT(Design Under Test) +with those data automatically at startup time. You must read +the tri-mode thernet spec-doc before setting the REG.Only the +correct configuration can make sitmulation continue.} + +set namelist { +RegName Address default Data} +set datalist { + +{Tx_Hwmark 0 0x001e 0x001e} +{Tx_Lwmark 1 0x0019 0x0019} +{pause_frame_send_en 2 0x0000 0x0000} +{pause_quanta_set 3 0x0000 0x0000} +{IFGset 4 0x001e 0x001e} +{FullDuplex 5 0x0001 0x0001} +{MaxRetry 6 0x0002 0x0002} +{MAC_tx_add_en 7 0x0000 0x0000} +{MAC_tx_add_prom_data 8 0x0000 0x0000} +{MAC_tx_add_prom_add 9 0x0000 0x0000} +{MAC_tx_add_prom_wr 10 0x0000 0x0000} +{tx_pause_en 11 0x0000 0x0000} +{xoff_cpu 12 0x0000 0x0000} +{xon_cpu 13 0x0000 0x0000} +{MAC_rx_add_chk_en 14 0x0000 0x0000} +{MAC_rx_add_prom_data 15 0x0000 0x0000} +{MAC_rx_add_prom_add 16 0x0000 0x0000} +{MAC_rx_add_prom_wr 17 0x0000 0x0000} +{broadcast_filter_en 18 0x0000 0x0000} +{broadcast_bucket_depth 19 0x0000 0x0000} +{broadcast_bucket_interval 20 0x0000 0x0000} +{RX_APPEND_CRC 21 0x0000 0x0000} +{Rx_Hwmark 22 0x001a 0x001a} +{Rx_Lwmark 23 0x0010 0x0010} +{CRC_chk_en 24 0x0000 0x0000} +{RX_IFG_SET 25 0x001e 0x001e} +{RX_MAX_LENGTH 26 0x2710 0x2710} +{RX_MIN_LENGTH 27 0x0040 0x0040} +{CPU_rd_addr 28 0x0000 0x0000} +{CPU_rd_apply 29 0x0000 0x0000} +{Line_loop_en 33 0x0000 0x0000} +{Speed 34 0x0004 0x0004} +} + +cd ../data + + if {[catch {open CPU.vec r} fileid]} { + set RegVector {} + } else { + set RegVector {} + gets $fileid line + while {[eof $fileid]==0} { + scan $line "%02x%02x%04x" counter addr NewValue + set y [search_add $addr] + if {$y!=-1} { + set x [lindex $datalist $y] + set x [lreplace $x 3 3 [format "0x%04x" $NewValue]] + set datalist [lreplace $datalist $y $y $x] + lappend RegVector "$y $NewValue" + } + gets $fileid line + } + close $fileid + + } + +toplevel .p +wm title .p "Setting Reg Data" +focus .p +frame .p.f1 +frame .p.f2 +pack .p.f1 .p.f2 -side top + +frame .p.f1.f1 +frame .p.f1.f2 +frame .p.f1.f3 +frame .p.f1.f4 +frame .p.f1.f5 +pack .p.f1.f1 .p.f1.f2 .p.f1.f3 .p.f1.f4 .p.f1.f5 -side left + +label .p.f1.f1.l100 -text [lindex $namelist 0] -fg blue +label .p.f1.f2.l100 -text [lindex $namelist 1] -fg blue -width 10 +label .p.f1.f3.l100 -text [lindex $namelist 2] -fg blue -width 5 +label .p.f1.f4.l100 -text [lindex $namelist 3] -fg blue -width 10 + +pack .p.f1.f1.l100 .p.f1.f2.l100 .p.f1.f3.l100 .p.f1.f4.l100 + +for {set i 0} {$i < [llength $datalist]} {incr i} { + label .p.f1.f1.l$i -text [lindex [lindex $datalist $i] 0] + label .p.f1.f2.l$i -text [lindex [lindex $datalist $i] 1] + label .p.f1.f3.l$i -text [lindex [lindex $datalist $i] 2] + entry .p.f1.f4.en$i -width 10 + .p.f1.f4.en$i insert 0 [lindex [lindex $datalist $i] 3] + if {[lindex [lindex $datalist $i] 2] !=[lindex [lindex $datalist $i] 3]} { + .p.f1.f4.en$i config -fg red + } + pack .p.f1.f1.l$i .p.f1.f2.l$i .p.f1.f3.l$i .p.f1.f4.en$i + bind .p.f1.f4.en$i <FocusOut> [list CheckModify .p.f1.f4.en$i $i ] +} + + +button .p.f2.b1 -text "Save" -width 10 -command {WriteVect CPU.vec} +button .p.f2.b2 -text "SaveAs" -width 10 -command {WriteVect [reg_save_as]} +button .p.f2.b3 -text "Exit" -width 10 -command {destroy .p} +button .p.f2.b4 -text "Help" -width 10 -command {print_help $help_strings} +pack .p.f2.b1 .p.f2.b2 .p.f2.b3 .p.f2.b4 -side left +bind .p.f2.b1 <ButtonPress> {focus .p} + + +} + +proc CheckModify {target_en index} { + global RegVector + global datalist + set data [$target_en get] + set NewValue "$index $data" + + + if {[info exists RegVector]} { + set counter [llength $RegVector] + for {set c 0} {$c<$counter} {incr c} { + if {[lindex [lindex $RegVector $c] 0]== $index} { + if {[lindex [lindex $datalist $index] 2]==$data} { + $target_en config -fg black + set RegVector [lreplace $RegVector $c $c] + } else { + set RegVector [lreplace $RegVector $c $c $NewValue] + } + return + } + } + } + if {[lindex [lindex $datalist $index] 3]==$data} { + return + } else { + $target_en config -fg red + set RegVector [lappend RegVector $NewValue] + } +} + +proc WriteVect {filename} { + global RegVector + global datalist + if {[info exists RegVector]} { + set counter [llength $RegVector] + if {[catch {open $filename w} fileid]} { + puts {failed to open vector file "$filename"} + destrop .p + } else { + for {set i 0} {$i < $counter} {incr i} { + set addr [lindex [lindex $datalist [lindex [lindex $RegVector $i] 0]] 1] + set NewValue [lindex [lindex $RegVector $i] 1] + puts $fileid [format "%02x%02x%04x" $counter $addr $NewValue] + } + close $fileid + unset RegVector + destroy .p + } + } else { + destroy .p + } +} + +proc reg_save_as {} { + global fileselect + fileselect + tkwait window .fileSelectWindow + if {$fileselect(canceled)==1} { + return + } elseif {$fileselect(selectedfile)==""} { + warning_message "file have not been selected!" + } else { + return $fileselect(selectedfile) + } +} + +proc search_add {addr} { + global datalist + set n 0 + foreach line $datalist { + if {[lindex $line 1]==$addr} { + return $n + } + incr n + } + return -1 +}
\ No newline at end of file diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl new file mode 100644 index 000000000..2bc42d7b5 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/set_stimulus.tcl @@ -0,0 +1,101 @@ +proc set_stimulus {} { + toplevel .stimulus + focus .stimulus + wm title .stimulus "Setting Stimulus Prameters" + + variable StartLength + variable EndLength + variable PacketNumber + variable Random + variable Broadcast + variable help_string + +set help_string { +Set Stimulus Help: + You can select to generate packet with sequential packet length or +random packet length. If you choise random packet length, the length of +generated packet will be a random value between the "Packet begin length" +to the "Packet end length". "Total Gen Packet number"is used to set the +number of packet will be generated as stimulus + As well, you can select "sequence" mode . The first Packet will be +generated with "Packet begin length",and the next Packet length will be +"Packet begin length" pluse one untile the packet length reach the value +of "Packet end length". Packet in each length will be generated according +to the value of "Packet number per length" } + + + if {[catch {open ../data/config.ini r} fileid]} { + set StartLength 46 + set EndLength 60 + set PacketNumber 1 + set Random 0 + set Broadcast 0 + } \ + else { + gets $fileid content + scan $content "%d,%d,%d,%d,%d" StartLength EndLength PacketNumber Random Broadcast + close $fileid + } + + frame .stimulus.f1 + label .stimulus.f1.lb -text "Packet begin length:" + entry .stimulus.f1.en -textvariable StartLength + pack .stimulus.f1 -fill x + pack .stimulus.f1.en .stimulus.f1.lb -side right + + frame .stimulus.f2 + label .stimulus.f2.lb -text "Packet end length:" + entry .stimulus.f2.en -textvariable EndLength + pack .stimulus.f2 -fill x + pack .stimulus.f2.en .stimulus.f2.lb -side right + + + frame .stimulus.f3 + label .stimulus.f3.lb -text "Packet number per length:" + entry .stimulus.f3.en -textvariable PacketNumber + pack .stimulus.f3 -fill x + pack .stimulus.f3.en .stimulus.f3.lb -side right + + frame .stimulus.f4 + radiobutton .stimulus.f4.1 -text "Sequence" -variable Random -value 0 \ + -command {.stimulus.f3.lb config -text "Packet number per length:"} + radiobutton .stimulus.f4.2 -text "Random" -variable Random -value 1 \ + -command {.stimulus.f3.lb config -text "Total Gen Packet number:"} + pack .stimulus.f4 -fill x + pack .stimulus.f4.1 .stimulus.f4.2 -side right + + frame .stimulus.f5 + checkbutton .stimulus.f5.1 -text "Broadcast" -variable Broadcast + pack .stimulus.f5 -fill x + pack .stimulus.f5.1 -side right + + frame .stimulus.f20 + button .stimulus.f20.1 -text "Save" -width 10 \ + -command { set fileid [open ../data/config.ini w 0600] + puts $fileid "$StartLength,$EndLength,$PacketNumber,$Random,$Broadcast" + close $fileid + destroy .stimulus + } + button .stimulus.f20.2 -text "Save as" -command {sti_save_as $StartLength $EndLength $PacketNumber $Random $Broadcast} -width 10 + button .stimulus.f20.3 -text "Cancel" -command {destroy .stimulus} -width 10 + button .stimulus.f20.4 -text "Help" -width 10 -command {print_help $help_string} + pack .stimulus.f20 -fill x + pack .stimulus.f20.1 .stimulus.f20.2 .stimulus.f20.3 .stimulus.f20.4 -side left +} + +proc sti_save_as {StartLength EndLength PacketNumber Random Broadcast} { + global fileselect + cd ../data + fileselect + tkwait window .fileSelectWindow + if {$fileselect(canceled)==1} { + return + } elseif {$fileselect(selectedfile)==""} { + warning_message "file have not been selected!" + } else { + set fileid [open $fileselect(selectedfile) w 0600] + puts $fileid "$StartLength,$EndLength,$PacketNumber,$Random,$Broadcast" + close $fileid + destroy .stimulus + } +}
\ No newline at end of file diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/start_verify.tcl b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/start_verify.tcl new file mode 100644 index 000000000..3209e6309 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/start_verify.tcl @@ -0,0 +1,127 @@ +proc start_verify {batch index} { +variable compiling +variable simulate_times +variable test_case_number +variable batch_data {} +variable batchmode +variable piple +############################################################################### + set batchmode $batch + toplevel .l + focus .l + wm title .l "Simulation Log" + frame .l.f1 + frame .l.f2 + pack .l.f1 .l.f2 -side top + + text .l.f1.t1 -width 80 -height 40 -yscrollcommand {.l.f1.scroll set} + + scrollbar .l.f1.scroll -command {.l.f1.t1 yview} + button .l.f2.b1 -text "Exit" -command {destroy .l} -width 10 + button .l.f2.b2 -text "Stop" -command {Stop_sim} -width 10 + pack .l.f1.scroll -side right -fill y + pack .l.f1.t1 + pack .l.f2.b1 .l.f2.b2 -side left + + set output_win .l.f1.t1 + set simulate_times 0 + set test_case_number [lindex $index 0] + cd ../bin + set compiling 1 + if {$batch==0} { + Run "bash sim.nc " $output_win + } elseif {[catch {open ../data/batch.dat r} fileid]} { + $output_win insert end "Failed open ../data/batch.dat file\n" + } elseif {[lindex $index 0] == "empty"} { + $output_win insert end "Not any test case was selected\n" + } else { + set i 0 + gets $fileid line + while {[eof $fileid]==0} { + lappend batch_data $line + gets $fileid line + incr i + } + $output_win insert end "Verifcation Started\n" + $output_win insert end "Starting Compiling Source file and libs......\n" + Run "bash com.nc" $output_win + close $fileid + } +} + +proc Run {command output_win} { + global piple + if [catch {open "|$command |& cat "} piple] { + $output_win insert end $piple\n + } else { + fileevent $piple readable [list Log $piple $output_win] + } +} + +proc Log {piple output_win} { + global compiling + global batchmode + set saparator "###################################################################\n" + if {[eof $piple]} { + if {$batchmode==0} { + $output_win insert end $saparator + $output_win insert end "end of Simulation....\n" + $output_win insert end $saparator + } elseif {$compiling==1} { + $output_win insert end $saparator + $output_win insert end "end of Compiling....\n" + $output_win insert end $saparator + $output_win insert end "\n \n \n" + set compiling 0 + sim_next_case + } else { + $output_win insert end $saparator + $output_win insert end "end of Testcase....\n" + $output_win insert end $saparator + $output_win insert end "\n \n \n" + sim_next_case + } + close $piple + } else { + gets $piple line + $output_win insert end $line\n + $output_win see end + } +} + +proc sim_next_case {} { + global test_case_number + global simulate_times + global batch_data + global index + set saparator "###################################################################\n" + set output_win .l.f1.t1 + set test_case_number [lindex $index $simulate_times] + if {$simulate_times < [llength $index]} { + set line [lindex $batch_data $test_case_number] + set source_sti [lindex $line 1] + set source_reg [lindex $line 2] + + if {$simulate_times==0 ||[file exists "../log/.sim_succeed"]} { + exec cp "../data/$source_sti" "../data/config.ini" + exec cp "../data/$source_reg" "../data/CPU.vec" + + $output_win insert end $saparator + $output_win insert end "starting test case :[lindex $line 0]....\n" + $output_win insert end $saparator + $output_win insert end "\n \n \n" + incr simulate_times + Run "bash sim_only.nc" $output_win + } else { + $output_win insert end "test_case :[lindex $line 0] simulation failed!!\n" + } + + } else { + $output_win insert end "All test_case passed simulation Successfully!!\n" + } +} + +proc Stop_sim {} { + global piple + catch {close $piple} +}
\ No newline at end of file diff --git a/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/user_lib.tcl b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/user_lib.tcl new file mode 100644 index 000000000..14b4302b8 --- /dev/null +++ b/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/script/user_lib.tcl @@ -0,0 +1,17 @@ +proc print_help {help_string} { + toplevel .help + frame .help.1 + message .help.1.1 -text $help_string -width 10c + frame .help.2 + button .help.2.1 -text "exit" -command {destroy .help} -width 10 + pack .help.1 .help.2 .help.1.1 .help.2.1 +} + +proc warning_message {warning_string} { + toplevel .warning + frame .warning.1 + message .warning.1.1 -text $warning_string -width 10c + frame .warning.2 + button .warning.2.1 -text "exit" -command {destroy .warning} -width 10 + pack .warning.1 .warning.2 .warning.1.1 .warning.2.1 +}
\ No newline at end of file |