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| author | matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5> | 2009-01-22 18:23:45 +0000 |
|---|---|---|
| committer | matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5> | 2009-01-22 18:23:45 +0000 |
| commit | 74aac5eea0da918a15f365a7ea3c0c37a9badf86 (patch) | |
| tree | e9d340b5a2900d334fcd8483487bce16f6d0fcd0 /opencores/aemb/rtl/verilog | |
| parent | cb10e89abd211ec37472d3b0e00903d67325096d (diff) | |
| download | uhd-74aac5eea0da918a15f365a7ea3c0c37a9badf86.tar.gz uhd-74aac5eea0da918a15f365a7ea3c0c37a9badf86.tar.bz2 uhd-74aac5eea0da918a15f365a7ea3c0c37a9badf86.zip | |
trial fix for problem when 3 loads with 1 wait state are followed by a barrel shift or multiply. Shawn will let us know if this works.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10290 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'opencores/aemb/rtl/verilog')
| -rw-r--r-- | opencores/aemb/rtl/verilog/aeMB_ibuf.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/opencores/aemb/rtl/verilog/aeMB_ibuf.v index b3e37c448..a4edf1d90 100644 --- a/opencores/aemb/rtl/verilog/aeMB_ibuf.v +++ b/opencores/aemb/rtl/verilog/aeMB_ibuf.v @@ -149,7 +149,7 @@ module aeMB_ibuf (/*AUTOARG*/ rSTALL <= 1'h0; // End of automatics end else begin - rSTALL <= #1 (!rSTALL & (fMUL | fBSF)) | (oena & rSTALL); + rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL); end endmodule // aeMB_ibuf @@ -189,4 +189,4 @@ endmodule // aeMB_ibuf New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code. -*/
\ No newline at end of file +*/ |