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| author | Lane Kolbly <lane.kolbly@ni.com> | 2022-03-18 15:45:47 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2022-03-23 16:14:07 -0500 |
| commit | 37987a87f49866b2d0b8b4aa90b20197ddcdad8d (patch) | |
| tree | e6fc3e24cbc87668e4f505fa0f070f0be9e63a9b /mpm | |
| parent | 48b76f49bc7e5498df4fba9274063913d7f31cfb (diff) | |
| download | uhd-37987a87f49866b2d0b8b4aa90b20197ddcdad8d.tar.gz uhd-37987a87f49866b2d0b8b4aa90b20197ddcdad8d.tar.bz2 uhd-37987a87f49866b2d0b8b4aa90b20197ddcdad8d.zip | |
mpm: x4xx: Remove GPIO classic mode register
Diffstat (limited to 'mpm')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py b/mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py index 0c283f8c0..3c001be5c 100644 --- a/mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py +++ b/mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py @@ -148,10 +148,6 @@ class DioControl: FULL_DIO_FPGA_COMPAT = (7, 5) - # DIO register addresses - RADIO_DIO_REGISTER_BASE = 0x8C000 - RADIO_DIO_CLASSIC_ATR_CONFIG_REGISTER = RADIO_DIO_REGISTER_BASE + 0x40 - # DIO registers addresses in CPLD CPLD_DIO_DIRECTION_REGISTER = 0x30 @@ -555,8 +551,6 @@ class DioControl: self, bank, self.FPGA_DIO_INTERFACE_DIO_SELECT_REGISTER) override_reg = self._GpioReg(self, bank, self.FPGA_DIO_OVERRIDE_REGISTER) sw_control_reg = self._GpioReg(self, bank, self.FPGA_DIO_SW_DIO_CONTROL_REGISTER) - classic_atr_config_reg = self._GpioReg( - self, bank, self.RADIO_DIO_CLASSIC_ATR_CONFIG_REGISTER) def get_gpio_src_i(gpio_pin_index): """ @@ -568,8 +562,8 @@ class DioControl: return f"DB{db}_SPI" else: db = int(radio_source_reg.get_pin(gpio_pin_index)) - ch = int(classic_atr_config_reg.get_pin(gpio_pin_index)) - return f"DB{db}_RF{ch}" + # Note that we can't distinguish between RF0 and RF1 + return f"DB{db}_RF0" else: if master_reg.get_pin(gpio_pin_index): if sw_control_reg.get_pin(gpio_pin_index): @@ -625,8 +619,6 @@ class DioControl: self, bank, self.FPGA_DIO_INTERFACE_DIO_SELECT_REGISTER) override_reg = self._GpioReg(self, bank, self.FPGA_DIO_OVERRIDE_REGISTER) sw_control_reg = self._GpioReg(self, bank, self.FPGA_DIO_SW_DIO_CONTROL_REGISTER) - classic_atr_config_reg = self._GpioReg( - self, bank, self.RADIO_DIO_CLASSIC_ATR_CONFIG_REGISTER) for pin_index, src_name in enumerate(src): pin_index = self._map_to_register_bit( @@ -646,7 +638,6 @@ class DioControl: channel = int(src_name[6]) override_reg.set_pin(pin_index, 0) radio_source_reg.set_pin(pin_index, slot) - classic_atr_config_reg.set_pin(pin_index, channel) else: source_reg.set_pin(pin_index, 0) if src_name in (self.X4XX_GPIO_SRC_PS, self.X4XX_GPIO_SRC_MPM): @@ -662,7 +653,6 @@ class DioControl: interface_select_reg.save() override_reg.save() sw_control_reg.save() - classic_atr_config_reg.save() # -------------------------------------------------------------------------- # Public API |